coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-12-05	soc/intel/common/lpc_lib: Add function to disable LPC Clock Run	Nico Huber
	Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-28	siemens/mc_apl1: Extend circuit life by clock gating and power gating	Mario Scheithauer
	The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-09	soc/intel/common: Enable decoding of the COMB range to LPC based on Kconfig	Subrata Banik
	By default all Intel platform has enable IO decode range for COMA if CONFIG_DRIVERS_UART_8250IO is selected. With this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection. Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid an additional pci configuration read to get the same data. Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-02-20	src/soc: Fix various typos	Jonathan Neuschäfer
	These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-01-17	soc/intel/common: Add option to pass SoC IO resource	Subrata Banik
	This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03	soc/intel/common/block: Update LPC lib	Ravi Sarawadi
	Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15	soc/intel/common/block: Add LPC Common code and use it for APL	Ravi Sarawadi
	Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>