| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-06-06 | soc/intel/common/block: Move gspi common functions into block/gspi | Subrata Banik | |
| This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/gspi. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
| 2017-04-06 | soc/intel/common: Add support for common GSPI controller | Furquan Shaikh | |
| Add support for GSPI controller in Intel PCH. This controller is compliant with PXA2xx SPI controller with some additional registers to provide more fine-grained control of the SPI bus. Currently, DMA is not enabled as this driver might be used before memory is up (e.g. TPM on SPI). Also, provide common GSPI config structure that can be included by SoCs in chip config to allow mainboards to configure GSPI bus. Additionally, provide an option for SoCs to configure BAR for GSPI controllers before memory is up. BUG=b:35583330 Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19098 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> | |||
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