coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-09-11	soc/intel/skylake: Fix SPI WP disable status check	Ravi Sarawadi
	Use SPI write protect disable bit from BIOS_CONTROL register to check write protect status. Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25	soc/intel/common: Add function to DLOCK PR registers	Barnali Sarkar
	Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09	soc/intel/common/fast_spi: support caching bios in ramstage	Aaron Durbin
	After the MTRR solution has been calculated provide a way for code to call the same function, fast_spi_cache_bios_region(), in all stages. This is accomplished by using the ramstage temporary MTRR support. Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20115 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-05	soc/intel/common/block: add bios caching to fast spi module	Aaron Durbin
	Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-05	soc/intel/common: Provide common block fast_spi_flash_ctrlr	Furquan Shaikh
	Now that we have a common block driver for fast spi flash controller, provide spi_ctrlr structure that can be used by different platforms for defining the bus-ctrlr mapping. Only cs 0 is considered valid. Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-01	soc/intel/common/block: Add Intel common FAST_SPI code	Barnali Sarkar
	Create Intel Common FAST_SPI Controller code. This code contains the code for SPI initialization which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h * Implement FAST_SPI read, write, erase APIs. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>