Age | Commit message (Collapse) | Author |
|
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/i2c.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H.
Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23382
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In ramstage the device_operations are needed for the i2c designware
host controller. Move the intel/common/block/i2c implementation
into the generic driver so other platforms can take advantage of it.
BUG=b:72121803
Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Rename the following functions to ensure it's clear that the designware
i2c host controller driver is the one that these functions are
associated with:
i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg()
i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base()
i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus()
i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn()
BUG=b:72121803
Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23371
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
We check for NULL from the return of function acpi_device_path
before passing it to acpigen_write_scope to avoid NULL pointer
dereference.
Change-Id: I997461c9b639acc3c323263d304333d3a894267c
Found-by: Klockworks
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/23094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:70232394
BRANCH=none
TEST=emerge-reef coreboot
emerge-glados
Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the
SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on
SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore,
remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency
for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG.
BUG=b:70232394
Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22874
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
|
|
This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.
TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e
Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Print error message when using common i2c without default clock defined.
TEST=Do not define default clock in Kconfig, compile will stop for
assertion.
Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Fix issues reported by coverity scan in the below files.
src/soc/intel/common/block/i2c
1375440: Improper use of negative value
1375441: Improper use of negative value
1375444: Improper use of negative value
src/soc/intel/apollolake/i2c.c
1375442: Unsigned compared against 0
Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Do not use the global platform_i2c_transfer() function that can only be
implemented by a single driver. Instead, make a `struct device` aware
transfer() function the only interface function for I2C controller dri-
vers to implement.
To not force the slave device drivers to be implemented either above
generic I2C or specialized SMBus operations, we support SMBus control-
lers in the slave device interface too.
We start with four simple slave functions: i2c_readb(), i2c_writeb(),
i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec-
tive SMBus functions. But we keep aliases because it would be weird to
force e.g. an I2C EEPROM driver to call smbus_read_byte().
Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add Cannonlake pci device ids for all the merged intel common code. As
of now only have CNL-U and CNL-Y pci ids.
Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency
was I2C_SPEED_FAST.
This was due to incorrect register programming.
TEST= Build for Soraka, I2C frequency during firmware execution was
I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS.
Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
If I2C device is disabled:
1. BAR for the device will be 0
2. There is no need to generate ACPI tables for the device
TEST=Verified that if an i2c device is disabled statically in
devicetree or dynamically in mainboard, then coreboot does not die
looking for missing resources.
Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Add GLK PCI IDs for I2C to use common I2C code.
Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/19782
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|