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path: root/src/soc/intel/common/block/gpio/gpio.c
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2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04soc/intel/common/block/gpio: add code for NMI enablingMichael Niewöhner
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04intel/common/block/gpio: only reset configured SMI instead of allMichael Niewöhner
Currently, when a SMI GPIO gets configured, the whole status register is get written back and thus, all SMIs get reset. Do it right and reset only the correspondig status bit of the GPIO to be configured. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03Change all assert(0) to BUG()Julius Werner
I would like to make assertions evaluate at compile time where possible, but sometimes people used a literal assert(0) to force an assertion in a certain code path. We already have BUG() for that so let's just replace those instances with that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-17intel/common: add a macro to set ownership for GPIMaxim Polyakov
Adds a new macro that allow to set the DRIVER or ACPI as host software ownership for the GPI pad using the parameter own. Thus, this macro can define more variants for pad configuration than others. This is necessary to describe in more detail the configuration for the Tioga Pass OCP server [1] and other boards. In addition, these changes will be used to automatically generate macros [2] and great simplify this task. [1] https://review.coreboot.org/c/coreboot/+/39427 [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I9c191fb6935e94da6e296f8fee0b91a973534e1a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-07soc/intel/common: gpio: print error if pad is not foundMaxim Polyakov
Allow to print a debug error message when the GPIO community does not contain the pad number from the motherboard configuration. Change-Id: I21fb389a5d29e11b1fbc24e836d91e17957047f1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-05-30soc/intel/common/block/gpio: Fix the mask for gpio_pm_configureFurquan Shaikh
gpio_pm_configure clears out all the bits related to PM configuration in MISCCFG register and sets only the bits requested by mainboard. The mask as it is set currently results in preserving all PM bits instead of clearing them. This change updates the mask to ensure that the PM bits are cleared before setting the ones requested by mainboard. Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-20soc/intel/common/block/gpio: Add gpio_pm_configure() functionSubrata Banik
This patch adds new function to perform gpio power management programming as per EDS. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: I816a70ad92595f013740a235a9799912ad51665e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29soc/intel/common: Add support to clear GPI IS & IE registersKarthikeyan Ramasubramanian
Add support to reset the GPI Interrupt Status & Enable registers so that the system does not experience any interrupt storm from a GPI when it comes out of one of the sleep states. BUG=b:130593883 BRANCH=None TEST=Ensure that the Interrupt status & enable registers are reset during the boot up. Ensure that the system boots fine to ChromeOS. Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11Kane Chen
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors. BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05src/soc/intel/common: Clear GPIO driver ownership when not requestedKeith Short
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested. BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully. Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24soc/intel/gpio: Enable configuring GPIO debounce durationKarthikeyan Ramasubramanian
Add new helper macros to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-14soc/intel/common: Add support for GPIO group pad baseDuncan Laurie
In some situations the GPIO pad numbers used by the OS are not contiguous and coreboot must provide a way for ACPI to provide the expected GPIO number to the OS. To do this each GPIO group can now have a pad base value, which will be used as the starting pin number for this group and it is added to the relative pin number of this GPIO to compute the ACPI pin number for a particular GPIO. By default this change has no effect because the existing uses of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the GPIO number is used as the ACPI pin number without translation. BUG=b:120686247 TEST=tested on a sarien(cannonlake) board Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30131 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-18soc/intel/.../Kconfig: Move GPIO debug option into debug menuNico Huber
Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the Debugging menu. Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-11soc/intel/common/block/gpio: check for NULL using if statementBora Guvendik
Remove assert() and instead use if statement to check if comm->groups is NULL. Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-26soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_overrideFurquan Shaikh
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. This is done to allow sharing of GPIO tables across baseboard-variants for various boards i.e. Each board can have a base config table which is provided by the baseboard and an optional override config table that can be provided by a variant to configure certain GPIOs differently. It is helpful when the variant GPIO diff list is not very huge compared to the baseboard. BUG=b:111743717 TEST=Verified that the GPIO config for phaser is same with and without this change. Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14soc/intel/denverton_ns: port gpio to intelblockJulien Viard de Galbert
The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-16soc/intel/common/block/gpio: Change group offset calculationBora Guvendik
Add group information for each gpio community and use it to calculate offset of a pad within its group. Original implementation assumed that the number of gpios in each group is same but that lead to a bug for cnl since numbers differ for each group. BUG=b:69616750 TEST=Need to test again on SKL,CNL,APL,GLK Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22571 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05soc/intel/common/block/gpio: Fix PAD_DW1_MASKHannah Williams
for case CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y https://ticket.coreboot.org/issues/128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I2b0b9c07ebc99f4b4d7e8c5a72483bedd33e2e07 Reviewed-on: https://review.coreboot.org/21282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/common/gpio: add helpers for relative pin calcuationsAaron Durbin
The gpio numbers are global, but they have their respective place within each community and the group within their community. For all the calculations open coding this calculation convert them to use the helpers. Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-20soc/intel/common/gpio: fix gpi_status_get()Aaron Durbin
A pad number is passed into gpi_status_get() to determine if its associated bit is set from a generated event. However, the implementation wasn't taking into account the gpi_status_offset which dictates the starting offset for each community. Additionally, the max_pads_per_group field is per community as well -- not global. Fix the code to properly take into account the community's gpi_status_offset as well as the max_pads_per_group. Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20652 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2017-07-17soc/intel/common/gpio: clean up logical to chipset mappingAaron Durbin
1. Explicitly add LOGICAL to the reset macro name to make it explicit that the values are logical. 2. Reword some of the comments and combine them into single comment instead of scattering the comments throughout. 3. Use c99 struct initializers for the reset mapping array. 4. For the chipset specific values use literals that match the hardware. 5. Use 'U' suffixes on the literals so we don't trip up compiler being over zealous on undefined behavior. 6. Use unsigned and fixed-width types for the reset mapping structure since the code is reliant on matching up with a register definition. 7. Fix formatting that can fit < 80 cols. Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-17soc/intel/common/gpio: distingiush single vs multi acpi devicesAaron Durbin
Sadly, small core and big core are not aligned with the OS driver's expectation on the number of ACPI devices used for each community. Big core uses a single device while small cores use one ACPI device per community. Allow for this distinction within the common gpio implementation and ensure apollolake is utilizing the new option to retain the correct behavior. Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20588 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-29soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams
Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 05:47:35 +0000