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2021-02-18soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` functionAngel Pons
Also remove one macro that was only used inside that function. Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08soc/intel/common/fast_spi: Add Lockdown of extended BIOS regionSrinidhi N Kaushik
This change adds support to Lock down the configuration of extended BIOS region. This is done as part of fast_spi_lockdown_cfg() so that it is consistent with the other lockdown. Change includes: 1. New helper function fast_spi_lock_ext_bios_cfg() added that will basically set EXT_BIOS_LOCK. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/fast_spi: Add extended decode window supportSrinidhi N Kaushik
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init(). Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-25soc/intel/common: Add function to DLOCK PR registersBarnali Sarkar
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/common/block: Modify fast_spi_lock_bar functionBarnali Sarkar
Use 16bit write to avoid touching the upper two bytes that may cause write cycle to fail in case a prior transaction has not completed. This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN, writing both in the same cycle is guaranteed to work by design. Avoid read->modify->write operation not to clear the RW1C bits unintentionally. Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24soc/intel/common/block: Add max SPI transaction time-out as 5 secBarnali Sarkar
Earlier 15ms time-out was kept for SPI transactions which was not enough for SPI Erase transactions. Increase the max time-out time to 5 secs which was present in SKL before common code. This increase in time-out won't disturb other SPI transactions like Read, Write or Read Status, since, for those it will come out of the loop once FDONE bit or FCERR bit is set. BUG=b:63959637 BRANCH=none TEST=Built and booted poppy and all SPI transactions succeeded. Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01soc/intel/common/block: Add Intel common FAST_SPI codeBarnali Sarkar
Create Intel Common FAST_SPI Controller code. This code contains the code for SPI initialization which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h * Implement FAST_SPI read, write, erase APIs. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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