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2020-12-14soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-08soc/intel/common/block/cpu/car: Fix two whitespace issuesSubrata Banik
This patch removes 1 unnecessary whitespace and add 1 whitespace into IA common car code block. Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 supportPatrick Rudolph
Doesn't affect x86_32. Tested on Intel Skylake. Boots into bootblock and console is working. Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-15soc/intel/common: Make alignment proper for commentsSubrata Banik
Change-Id: If932582d03bb2f6d3d14c9bce45cf2030f3b3c4e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-12soc/intel/common: Fix typo mistake in cache_as_ram.SSubrata Banik
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-04-21cpu/x86: Move checking for MTRR's as a proxy for proper CPU resetArthur Heymans
Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset is common across multiple platforms. Therefore place it in a common location. Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-10-16intel/common: CAR setup CQOSNaresh G Solanki
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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