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Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.
There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
causes problems with cbfs_mcache)
Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.
APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.
Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.
Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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postcar stage does not consume cpulib.c, so don't include it there.
Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is done in postcar stage. This also assumes CAR tear down will
always be done in postcar stage.
Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset
is common across multiple platforms. Therefore place it in a common
location.
Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create Intel Common CPU library code which provides various
CPU related APIs.
This patch adds cpulib.c file which contains various helper
functions to address different CPU functionalities like -
cpu_set_max_ratio(),
cpu_get_flex_ratio(),
cpu_set_flex_ratio(),
cpu_get_tdp_nominal_ratio(),
cpu_config_tdp_levels(),
cpu_set_p_state_to_turbo_ratio(),
cpu_set_p_state_to_nominal_tdp_ratio(),
cpu_set_p_state_to_max_non_turbo_ratio(),
cpu_get_burst_mode_state(),
cpu_enable_burst_mode(),
cpu_disable_burst_mode(),
cpu_enable_eist(),
cpu_disable_eist(),
cpu_enable_untrusted_mode()
Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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