coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-12-16	soc/intel/common/block/chip/Kconfig: Fix minor whitespace	Himanshu Sahdev aka CunningLearner
	Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: RONAK KANABAR <ronak199323@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-06-06	soc/intel/common/block: Add common chip config block	Subrata Banik
	Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>