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In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in
ramstage to fix build error.
BRANCH=firmware-brya-14505.B
Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch renames identifiers (macros, function and structure names) in
the basecode/debug/debug_feature.c to generic names so that they can be
used to control the features which may have to be controlled either
during pre and post memory.
Currently, the naming of identifiers indicate that it meant to control
the features which can be controlled during only pre-memory phase.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch uses coreboot error codes instead of uint8_t data type in the
pre_mem_debug_init function.
TEST=build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I957ff764900cb789bf2aacf0472dcb281f48af07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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The patch adds support to control CSE Lite firmware update dynamically.
In order to disable the CSE firmware update functionality, offset 0xf00
in the coreboot binary be updated with 0x1.
Run below command on the binary to disable CSE firmwar update
printf '\x01' | dd of=image-brya4es.serial.bin bs=1 seek=3840 count=1
conv=notrunc
BUG=b:153410586
TEST=Verified CSE firmware update functionality is not getting
triggered after updating the offset:0xF00 in the coreboot binary.
........................ CB Logs ......................................
[DEBUG] prev_sleep_state 5
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
[DEBUG] cse_lite: Flags = 0x3
[DEBUG] cse_lite: RO version = 16.0.15.1752 (Status=0x0, Start=0x2000,
End=0x19bfff)
[DEBUG] cse_lite: RW version = 16.0.15.1752 (Status=0x0,
Start=0x205000, End=0x439fff)
rt_debug: pre_mem_debug.cse_fw_update_disable=1
[DEBUG] Boot Count incremented to 956
.......................................................................
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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The patch fixes the buggy code which tries to access the Descriptor
Region. The existing code doesn't use correct APIs to access the
Descriptor Region. Hence, error message is getting displayed during
the boot.
BUG=b:229003612
TEST=Build and verify no errors seen while accessing the Descriptor
Region.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding coreboot.
In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.
The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).
BUG=b:153410586
BRANCH=None
TEST=Verified CSE firmware update functionality on brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the
source statement.
Also, no kconfig files under src/soc/intel/common/basecode/. Clean
that up.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Expand the scope of 'common/basecode' directory to keep common
non-IP code block (like acpi, power limit).
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7a2778704016b501eb20382d4603295cec8375d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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