coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-10-29	soc/intel/common: Add reset.c to postcar	Furquan Shaikh
2016-10-26	soc/intel/common: Enable support to write protect SPI flash range	Furquan Shaikh
2016-08-01	soc/intel/common: Enable MTRR display during bootblock & postcar	Lee Leahy
2016-07-28	soc/intel/skylake: Add C entry bootblock support	Subrata Banik
2016-06-29	soc/intel/{common,skylake}: provide common NHLT SoC support	Aaron Durbin
2016-06-09	soc/intel/common: Add LPSS I2C driver	Duncan Laurie
2016-06-08	soc/intel/common: Add common code for acpi c/p/t-state entries	Hannah Williams
2016-05-25	soc/intel/common: Add common smihandler code	Hannah Williams
2016-05-18	soc/intel/common: Add IGD OpRegion support	Andrey Petrov
2016-05-18	soc/intel/common: Add utility to load VBT file	Andrey Petrov
2015-11-20	intel: Add MMA feature in coreboot	Pratik Prajapati
2015-10-27	FSP 1.1: Move common FSP code	Lee Leahy
2015-10-11	skylake: add support for verstage	Aaron Durbin
2015-09-17	intel/common: Add common code for filling out ACPI _SWS	Duncan Laurie
2015-08-29	soc/intel/common: Add mrc.cache file to CBFS when appropriate	Alexandru Gagniuc
2015-08-14	intel/common: fix stage_cache_external_region()	Aaron Durbin
2015-06-24	Intel Common SOC: Add romstage support	Lee Leahy
2015-04-30	kbuild: Don't require intel/common changes for every soc	Stefan Reinauer
2015-04-29	kbuild: automatically include SOCs	Stefan Reinauer
2015-04-18	soc/intel/common: Add common reset code	Lee Leahy
2014-10-22	baytrail: Move HDA verb table to Intel SOC common directory	Duncan Laurie
2014-10-22	baytrail: Move MRC cache code to a common directory	Duncan Laurie