coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-09-17	intel/common: Add common code for filling out ACPI _SWS	Duncan Laurie
2015-08-29	soc/intel/common: Add mrc.cache file to CBFS when appropriate	Alexandru Gagniuc
2015-08-21	soc/intel/common: CACHE_MRC_SETTINGS doesn't depend on HAVE_MRC	Martin Roth
2015-08-14	intel/common: use external stage cache for fsp_ramstage	Aaron Durbin
2015-08-13	soc/common/intel: Reset is not dependend upon FSP	Lee Leahy
2015-07-21	intel fsp: remove CHIPSET_RESERVED_MEM_BYTES	Aaron Durbin
2015-06-26	soc/intel/common: Restrict common romstage/ramstage code to FSP	Lee Leahy
2015-06-25	soc/intel/common/Kconfig: Fix warning & whitespace	Martin Roth
2015-06-24	Intel Common SOC: Add romstage support	Lee Leahy
2015-04-30	kbuild: Don't require intel/common changes for every soc	Stefan Reinauer
2015-04-18	soc/intel/common: Add common reset code	Lee Leahy
2015-04-18	soc/intel/common: Add function to protect MRC cache	Duncan Laurie
2014-10-22	baytrail: Move MRC cache code to a common directory	Duncan Laurie