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Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.
TEST=N/A
Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
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Add common i2c support for cannonlake.
TEST=N/A
Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos"). Avoid this bug in the future.
Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch uses common SCS library to set up sd card.
Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add common p2sb driver support.
TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.
Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds the C state and P state configurations for
cannonlake soc.
TEST = Boot and test the CPU states for all the cores are
present in "powertop" tool output.
Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Common PMC code comes with its own.
Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092
Increase the stack size from 4kiB to 8kiB to prevent stack overrun.
TEST=No stack overrun is observed and it boots to OS properly.
Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cannonlake SOC support up to 16 PCI express root port.
BUG=CID 1381813;1381814;
Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Include common platform.asl to have generic indication of power
transition state of system.
TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.
Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
needed for CNL.
TEST=Pre-OS screen comes up and VBT is getting passed to kernel.
Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add option for user to select what kind of probe can be used for
platform debug.
TEST=Set to XDP and boot up system with XDP hooked, able to halt.
Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21942
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.
TEST=NONE
Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements soc override function to calculate reserve memory
size (PRMRR, ME stolen, PTT etc). System memory should reserve those
memory ranges.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.
Change-Id: I3052a255c4496dc81c8dfc6882d3ad504abae9c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.
usable memory start = TOLUD - Generic memory size -
- soc specific reserve memory size.
Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses PMC common function to get previous sleep state
using cbmem or chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Update gpe handling function names to explicitly mention if they
are operating on:
a. STD GPE events
b. GPIO GPE events
c. Both
2. Update comment block in pmclib.h to use generic names for STD and
GPIO GPE registers instead of using any one platform specific names.
BUG=b:67712608
Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21968
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST = Boot to OS, check if pinctrl probed successfully
Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Add the required ACPI sleep states
Change-Id: I7750062554f087e4f88da56790e4122d5fa20529
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21975
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Set default UART number to 2 if 32bit PCI got selected, the proper debug
print can be seen from serial port in case of switch between platforms,
especially when change to lpss uart from legacy uart or vise versa.
Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21544
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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That removes the need for another global variable.
Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21907
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.
Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable MRC cache by default.
TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.
Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Reduce the bootblock size to 16KiB from the default 64KiB.
Not all that space is necessary.
Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add all the SOC level DSDT tables, reference from skylake/kabylake.
Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TEST=Boot to OS
Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21758
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Disable CPU Ratio override as input to FSP Memory init.
Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add ACPI methods for gpio, scs and pcr.
TEST=Boot to OS.
Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI dsdt table for northbridge, report proper resources in dsdt
entries.
TEST=Boot up into OS fine.
Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1.Add common ITSS support as part of LPC driver init code.
2.Add LPC pci driver for CNL
Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Add FSP GOP config.
2. Pass VBT to FSP.
Change-Id: Icf836d683ae00cd034c853bc9ce965d4de5f7413
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In coreboot commit bcd0bdabed (soc/intel/cannonlake: add rtc failure
checking), the function soc_get_rtc_failed was supposed to be moved,
but the old function was not removed, causing a build error.
BUG=b:63054105
Change-Id: I31c1966af413df3f5a5492a5dd891a6eb26a1fc4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred. In addition actually
provide soc_get_rtc_failed() which properly indicates to the common
code that RTC failure did occur in the cmos_init() path.
BUG=b:63054105
Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add PMC pci driver on top of PMC common code, also include pmc init code
reference from skylake.
Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define USB2, USB3 and Type-C configuration for CannonLake.
Change-Id: I42243950366d672e886158eb1934350f47b4ff1f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add SerialIO device mode configuration, device mode definition mirrored
from FSP.
Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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There was already a uart.c added to bootblock. Remove the
duplicate addition.
Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch fixes klocwork bug due to recent memmap.c
implementation where “Pointer 'dev' returned from call
to function 'dev_find_slot' at line 144 may be NULL.”
Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch overrides default FSP IGD stolen memory size
UPD value.
TEST=Ensures FSP-M UPD “IgdDvmt50PreAlloc” value is 0x2 (64MB)
Change-Id: I63d992e139810ad203137b34c98d1a463f88b92d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use mca_configure() API from cpulib to configure
Intel Machine Check Architecture (MCA)
Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,
*** CID 1380036: Control flow issues (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>> CID 1380036: Control flow issues (NO_EFFECT)
>>> "i" is converted to an unsigned type because it's compared to an unsigned constant.
80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81 if (config->PcieRpEnable[i])
82 mask |= (1 << i);
Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adds spi.c and gspi.c to verstage.
Change-Id: I363d9aafa989c5a7a0b36ad9edf1c70a75604d28
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adds gpio.c to romstage and ramstage.
Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS.
Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.
Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot cannonlake RVP successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
6. Enable C6 DRAM with PRMRR size 0MB and boot to OS.
Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to avoid build bot hang issue due to no
active default value for UART_FOR_CONSOLE kconfig
option.
Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21287
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures coreboot can set PRMRR size and C6DRAM
enable FSP-M UPDs.
Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add return in case of null pointer to avoid coverity scan error, fixed
1.Coverity ID 1379849: Null pointer dereferences (FORWARD_NULL)
2.Coverity ID 1379848: Null pointer dereferences (FORWARD_NULL)
Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Now that there is a handy macro utilize it.
Change-Id: I560bc7a591075235229952cdea63d4e667f323ee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Initialize UPD params based upon config
Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21175
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial MP init support. This boots up all CPUs.
Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Populate soc_intel_cannonlake_config
- Add usb.h and vr_config.h for CannonLake
Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add SPI driver code for the SPI flash controller, including both
fast_spi and generic_spi.
Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add callbacks for initial PCI devices enumeration.
Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.
Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581
Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis
are put around the parameter expansion.
Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch to make code cleaner and remove unused systemagent
register macros. [same as KBL implementation]
Change-Id: I13b9c83097fc98183ea138c9087b5fc7834efd58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As per GCC 7.1 compiler struct reset_reply is considered
as uninitialized inside send_heci_reset_message function.
Change-Id: I01b95d31bfb1d2e9af1704a28dacb9cfd1cdcb50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.
Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add all missing _PCH_DEV definitions to pci_devs.h
Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Revere memory resource within SA, also perform necessary routine for
initialization during ramstage.
Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Calculate the top of ram from output of Fsp reserved memory range.
Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Look and feel update, sort the sequence in Kconfig.
Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.
Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The variable p was going out of scope while still being pointed to by
*cpu_name.
Fix coverity ID 1378215 (Pointer to local outside scope)
Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d.
This was merged too early. I'll repost it.
Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Initialize postcar frame once finish FSP memoryinit
Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Relocate ramstage into CBMEM.
Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Microcode needs to be loaded prior to FSP initialization.
Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Replace outdated defination of TCO_EN to TCO_BASE_EN
2.Remove setmaxfreq() as not needed any more.
Change-Id: Id54fdfd14f1abaa592132195e6f9acfa5807626e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add register definitions used in PMC block.
Change-Id: I963f402a59d49dfc7b76224f719a315e1cc6dc74
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20071
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It should never be globally exposed. Remove it.
Change-Id: I90e201ddd4df2cda89e7d3e4cb81bdc2a81cac83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add reset functionality. This implementation relies on CSE to trigger
global reset.
Change-Id: I7e6ae07a48f1cdc3d2f4cdb74246627d27253adf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This enables building working bootblock and non-functional romstage
and ramstage.
Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add essential initialization needed for PCH in bootblock.
Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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