coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-09-01	soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode	Lijian Zhao
2017-09-01	soc/intel/cannonlake: Perform dram top calculation based on HW registers	Subrata Banik
2017-08-30	soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLE	Subrata Banik
2017-08-30	soc/intel/cannonlake: Add PrmrrSize and C6DRAM config	Subrata Banik
2017-08-29	soc/intel/cannonlake: Fix Coverity scan error	Lijian Zhao
2017-08-26	soc/intel/cannonlake: use __packed	Aaron Durbin
2017-08-25	soc/intel/cannonlake: Init UPD params based on config	Pratik Prajapati
2017-08-24	soc/intel/cannonlake: Add cpu.c and MP init support	Pratik Prajapati
2017-08-22	soc/intel/cannonlake: Define soc_intel_cannonlake_config	Pratik Prajapati
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-21	soc/intel/cannonlake: Add support for all UART port index	Subrata Banik
2017-08-21	soc/intel/cannonlake: Add Kconfig option to select UART index	Subrata Banik
2017-08-17	soc/intel/cannonlake: Add SPI flash controller driver	Lijian Zhao
2017-08-17	intel/cannonlake/chip: Add initial PCI enum support	Pratik Prajapati
2017-08-16	soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode	Subrata Banik
2017-08-15	soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition	Subrata Banik
2017-08-15	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-08-15	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-08-15	soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macro	Aaron Durbin
2017-08-14	soc/intel/cannonlake: Remove unused systemagent registers	Subrata Banik
2017-08-14	soc/intel/cannonlake: Initialize struct member to 0	Subrata Banik
2017-08-11	soc/cannonlake: Enable SMM code for Cannon Lake	Brandon Breitenstein
2017-08-11	soc/intel/cannonlake: Add missing _PCH_DEV definitions	Furquan Shaikh
2017-08-09	soc/intel/cannonlake: Add ramstage SystemAgent support	Lijian Zhao
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao
2017-08-03	soc/intel/cannonlake: Sort Kconfig for Cannonlake	Lijian Zhao
2017-07-27	soc/intel/cannonlake: Correct gpio definition	Lijian Zhao
2017-07-24	Update files with no newline at the end	Martin Roth
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-07-22	soc/intel/cannonlake: Keep variable from going out of scope	Martin Roth
2017-07-21	Revert "soc/intel/cannonlake: Add postcar stage support"	Martin Roth
2017-07-21	Revert "soc/intel/cannonlake: Call into FSP siliconinit"	Martin Roth
2017-07-21	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-07-21	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-07-20	soc/intel/cannonlake: Make ramstage relocatable	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add microcode support	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Fix Build break	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Use common GPIO driver	Andrey Petrov
2017-07-18	soc/intel/cannonlake: Add PMC headers	Andrey Petrov
2017-07-17	soc/intel/cannonlake: remove top_of_32bit_ram() declaration	Aaron Durbin
2017-07-13	soc/intel/cannonlake: Add reset.c	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add Makefile	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add bootblock PCH	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add early CPU initialization	Andrey Petrov
2017-07-12	soc/intel/cannonlake: Add PCI dev macros and IDs	Andrey Petrov
2017-07-12	soc/intel/cannonlake: Add report_platform.c	Andrey Petrov
2017-07-02	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add UART initialization	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add initial dummy directory	Lijian Zhao