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path: root/src/soc/intel/cannonlake
AgeCommit message (Expand)Author
2019-05-01mb/google/sarien: Disable S5 wake on LAN by defaultEric Lai
2019-04-30vboot: refactor OPROM codeJoel Kitching
2019-04-29soc/intel: Add GPI interrupt config register offset infoKarthikeyan Ramasubramanian
2019-04-29soc/intel/cannonlake: Modify dq_map to provide for 6 entriesPaul Fagerburg
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
2019-04-253rdparty/fsp: Update submodule pointer to upstream masterMatt DeVillier
2019-04-23soc/intel/cannonlake: add missing console.h includePatrick Georgi
2019-04-23soc/intel/cannonlake: Enable PlatformDebugConsent by KconfigKane Chen
2019-04-23soc/intel/cannonlake: Add null reference check for Cnvi and XdciAamir Bohra
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
2019-04-22Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"Lijian Zhao
2019-04-19soc/intel/cannonlake: Add report for iGD 0x3ea1Lijian Zhao
2019-04-18soc/intel/cnl: Generate DMAR ACPI tableJohn Zhao
2019-04-16soc/intel/cannonlake: Configure Vmx support using KconfigRonak Kanabar
2019-04-16soc/intel/cannonlake: Implement soc side VMX supportRonak Kanabar
2019-04-16soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CMLSubrata Banik
2019-04-13soc/intel/cpulib: Remove redundent enable/disable functionsSubrata Banik
2019-04-12soc/intel/cannonlake: Select FSP_M_XIPFurquan Shaikh
2019-04-12soc/intel/cannonlake: Do not use XIP_ROM_SIZEFurquan Shaikh
2019-04-11soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groupsAamir Bohra
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
2019-04-08src/soc/intel/cannonlake: Remove ITSS IPC restoreAamir Bohra
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
2019-04-01soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetreeKrishna Prasad Bhat
2019-03-29soc/intel/cannonlake: Ignore GBE LTRLijian Zhao
2019-03-28soc/intel/cannonlake: Update CPU Ratio base on MSRLijian Zhao
2019-03-27soc/intel/cannonlake: Configure voltage margining policiesKrzysztof Sywula
2019-03-25soc/intel/cannonlake: Clear PMCON status bitsKrishna Prasad Bhat
2019-03-24soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik
2019-03-22soc/intel/cannonlake: Enable power button smi in pre-OSKrzysztof Sywula
2019-03-21soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-20soc/intel/cannonlake: Fix return values for get_param_valueFurquan Shaikh
2019-03-18soc/intel/cannonlake: Pass coreboot debug interface info to FSPMaulik V Vaghela
2019-03-16soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
2019-03-15soc/intel/cannonlake: Fix GEN_PMCON bit checksFurquan Shaikh
2019-03-13soc/intel/cannonlake: Allow mainboard to override DRAM part numberFurquan Shaikh
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-07soc/intel/cannonlake: Add support for logging wake source in SMMV Sowmya
2019-03-07soc/intel/cannonlake: Move power_state functions to pmutil.cV Sowmya
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-04soc/intel/cannonlake: Move common definitions to a header fileRizwan Qureshi
2019-03-04soc/intel/cnl/acpi: add ish ACPI deviceJett Rink
2019-03-04soc/intel/cannonlake: Fix DSDT compile remarksLijian Zhao
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-02-28soc/intel/cannonlake: Add CometLake SoC supportSubrata Banik
2019-02-28soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exitFurquan Shaikh
2019-02-28soc/intel/cannonlake: Add PCH series check for CML LP PCHMaulik V Vaghela
2019-02-28soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
2019-02-27soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_initFurquan Shaikh
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
2019-02-26soc/intel/common: Include cometlake PCH IDsRonak Kanabar
2019-02-24soc/intel/common: Include cometlake SA IDsRonak Kanabar
2019-02-24soc/intel/common: Include cometlake CPU IDsRonak Kanabar
2019-02-23soc/intel/cannonlake: Make few more whitespace proper in MCH nameSubrata Banik
2019-02-22soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device...Jeremy Soller
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
2019-02-22soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD nameSubrata Banik
2019-02-21soc/intel/cannonlake: SoC specific microcode update checkRonak Kanabar
2019-02-21soc/intel/cannonlake: Add field to identify single channel memoryShelley Chen
2019-02-21src/soc/intel/cannonlake: Add PsysPmax settingGaggery Tsai
2019-02-20src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao
2019-02-19soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao
2019-02-18soc/intel: Add mem_rank info in SMBIOSFrancois Toguo
2019-02-15soc/intel/cannonlake: Define VR settingsRoy Mingi Park
2019-02-13soc/intel/cannonlake: Configure serial debug uartRonak Kanabar
2019-02-13soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans
2019-02-07soc/intel/cannonlake: Configure GPIOs again after FSP-S is doneFurquan Shaikh
2019-02-07soc/intel/cannonlake: Add Whiskeylake SoC kconfigSubrata Banik
2019-02-04soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT KconfigSubrata Banik
2019-01-31soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ixRonak Kanabar
2019-01-28src/soc/intel/cnl/chip.h: Fix preprocessor conditionAngel Pons
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
2019-01-25soc/intel/cannonlake: Disable CpuRatio and SaGv in recoveryDuncan Laurie
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
2019-01-17soc/intel/cannonlake: drop extra newlinePatrick Georgi
2019-01-17soc/intel/cannonlake: Change in SaGv optionsRonak Kanabar
2019-01-16soc/intel/cannonlake: Fix afterg3 programmingLijian Zhao
2019-01-16soc/intel/cannonlake: Access conf pointer only if its not nullPratik Prajapati
2019-01-16soc/intel/cannonlake: Add processor power limits control supportSumeet Pawnikar
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2019-01-14soc/intel/cannonlake: Provide interface to update TCC offsetJohn Su
2019-01-12soc/intel/cannonlake: Hook up MicrocodeLijian Zhao
2019-01-10soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TOPatrick Georgi
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
2019-01-10Untangle CBFS microcode updatesNico Huber
2019-01-09soc/intel: Clean mess around UART_DEBUGNico Huber
2019-01-09soc/intel/cannonlake: Enable/Disable IPU based on devicetree switchV Sowmya
2019-01-08soc/intel/cannonlake: Add FSP UPD for minimum assertion widthDuncan Laurie
2019-01-08soc/intel/cannonlake: Add chipset event loggingDuncan Laurie
2019-01-08soc/intel/cannonlake: Fix chipset_power_state structureDuncan Laurie
2019-01-07soc/intel: Standardize names of common MSRsElyes HAOUAS