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path: root/src/soc/intel/cannonlake
AgeCommit message (Expand)Author
2017-09-01soc/intel/canonlake: Enable LPSS UART in 32bit PCI modeLijian Zhao
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
2017-08-30soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik
2017-08-29soc/intel/cannonlake: Fix Coverity scan errorLijian Zhao
2017-08-26soc/intel/cannonlake: use __packedAaron Durbin
2017-08-25soc/intel/cannonlake: Init UPD params based on configPratik Prajapati
2017-08-24soc/intel/cannonlake: Add cpu.c and MP init supportPratik Prajapati
2017-08-22soc/intel/cannonlake: Define soc_intel_cannonlake_configPratik Prajapati
2017-08-21soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao
2017-08-21soc/intel/cannonlake: Add support for all UART port indexSubrata Banik
2017-08-21soc/intel/cannonlake: Add Kconfig option to select UART indexSubrata Banik
2017-08-17soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao
2017-08-17intel/cannonlake/chip: Add initial PCI enum supportPratik Prajapati
2017-08-16soc/intel/cannonlake: Add proper support to enable UART2 in 16550 modeSubrata Banik
2017-08-15soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
2017-08-15soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
2017-08-14soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik
2017-08-14soc/intel/cannonlake: Initialize struct member to 0Subrata Banik
2017-08-11soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein
2017-08-11soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh
2017-08-09soc/intel/cannonlake: Add ramstage SystemAgent supportLijian Zhao
2017-08-07soc/intel/cannonlake: Add memory map supportLijian Zhao
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
2017-07-24Update files with no newline at the endMartin Roth
2017-07-24Fix files with multiple newlines at the end.Martin Roth
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
2017-07-20soc/intel/cannonlake: Make ramstage relocatableLijian Zhao
2017-07-19soc/intel/cannonlake: Add minimal changes to call FSP MemoryinitLijian Zhao
2017-07-19soc/intel/cannonlake: Add microcode supportLijian Zhao
2017-07-18soc/intel/cannonlake: Fix Build breakLijian Zhao
2017-07-18soc/intel/cannonlake: Use common GPIO driverAndrey Petrov
2017-07-18soc/intel/cannonlake: Add PMC headersAndrey Petrov
2017-07-17soc/intel/cannonlake: remove top_of_32bit_ram() declarationAaron Durbin
2017-07-13soc/intel/cannonlake: Add reset.cAndrey Petrov
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao