| Age | Commit message (Expand) | Author |
|---|
| 2019-08-02 | soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled | Aamir Bohra |
| 2019-08-02 | soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage | Subrata Banik |
| 2019-08-02 | soc/intel/common/pch: Move thermal kconfig selection into common/pch | Subrata Banik |
| 2019-08-01 | soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers | David Wu |
| 2019-07-31 | soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlake | Aamir Bohra |
| 2019-07-31 | soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix | Sumeet Pawnikar |
| 2019-07-30 | soc/intel/cnl: Only print ME status one time | Tim Wawrzynczak |
| 2019-07-30 | soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown | Subrata Banik |
| 2019-07-30 | soc/intel/cannonlake: Add new PCI IDs | Felix Singer |
| 2019-07-30 | soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds reads | Jacob Garber |
| 2019-07-29 | soc/intel/cannonlake: Correct the data type of serial_io_dev | Aamir Bohra |
| 2019-07-25 | soc/intel: Guard remaining SA_DEV_ROOT definition | Kyösti Mälkki |
| 2019-07-25 | soc/intel/cannonlake: Split the "internal PME" wake-up into more detail | Paul Fagerburg |
| 2019-07-21 | soc/intel: Expand SA_DEV_ROOT for ramstage | Kyösti Mälkki |
| 2019-07-21 | soc/intel: Fix chip_info for PCH_DEV_PMC | Kyösti Mälkki |
| 2019-07-19 | soc/intel/common: Add SOC specific function to get XHCI USB info | Karthikeyan Ramasubramanian |
| 2019-07-18 | soc/intel: Use config_of() | Kyösti Mälkki |
| 2019-07-18 | soc/intel: Use config_of_path(SA_DEVFN_ROOT) | Kyösti Mälkki |
| 2019-07-17 | soc/intel/cannonlake: Add device Ids for new CFL SKUs support | Lean Sheng Tan |
| 2019-07-17 | soc/intel: Fix regression with hidden PCI devices | Kyösti Mälkki |
| 2019-07-16 | soc/intel/{cnl,icl}: Always use CAR NEM enhanced by default | Angel Pons |
| 2019-07-15 | intel/cannonlake: Fix indentation | Kyösti Mälkki |
| 2019-07-13 | soc/intel/cannonlake: Remove unused header files from southbridge.asl | Aamir Bohra |
| 2019-07-13 | cpu/x86: Move smm_lock() prototype | Kyösti Mälkki |
| 2019-07-13 | soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP | Nico Huber |
| 2019-07-12 | soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id | Nico Huber |
| 2019-07-12 | soc/intel/common: Add CM246 LPC device id | Nico Huber |
| 2019-07-11 | soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASL | Tim Wawrzynczak |
| 2019-07-11 | soc/intel/cannonlake: Make EC S0ix notification optional in LPIT | Tim Wawrzynczak |
| 2019-07-11 | soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer | Subrata Banik |
| 2019-07-10 | soc/intel: Remove invalid smm_relocate stubs | Kyösti Mälkki |
| 2019-07-09 | arch/x86: Flip HAVE_MONOTONIC_TIMER default | Kyösti Mälkki |
| 2019-07-09 | cpu/x86: Flip SMM_TSEG default | Kyösti Mälkki |
| 2019-07-07 | soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage | Furquan Shaikh |
| 2019-07-07 | soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param | Furquan Shaikh |
| 2019-07-07 | soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC | Furquan Shaikh |
| 2019-07-06 | soc/intel/cannonlake: Fix outb order | Jeremy Soller |
| 2019-07-06 | soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value | Subrata Banik |
| 2019-07-05 | soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H | Jeremy Soller |
| 2019-07-04 | soc/intel: Replace uses of dev_find_slot() | Kyösti Mälkki |
| 2019-07-04 | arch/x86: Adjust size of postcar stack | Kyösti Mälkki |
| 2019-07-02 | soc/intel/cannonlake: Add support to log XHCI wake events | Paul Fagerburg |
| 2019-07-01 | Use 3rdparty/intel-microcode | Arthur Heymans |
| 2019-06-28 | soc/intel/cannonlake: fix use of legacy 8254 timer | Matt DeVillier |
| 2019-06-26 | soc/intel/cannonlake/Kconfig: Don't have all variants select SOC_INTEL_CANNON... | Arthur Heymans |
| 2019-06-21 | soc/intel: Provide SPD manufacturer ID and module type to SMBIOS | Duncan Laurie |
| 2019-06-21 | soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE | Arthur Heymans |
| 2019-06-13 | soc/intel/{cml, whl}: Add option to skip HECI disable in SMM | Subrata Banik |
| 2019-06-12 | vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 | Aamir Bohra |
| 2019-06-07 | soc/intel/cannonlake: Add _DSM method for SD controller | V Sowmya |
| 2019-06-06 | src/soc/intel/common/smbios: Add addtional infos to dimm_info | Christian Walter |
| 2019-06-04 | soc/intel/cannonlake: Do not read SPD again if index hasn't changed | Furquan Shaikh |
| 2019-06-03 | soc/intel: Replace UART_BASE() and friends with a Kconfig | Nico Huber |
| 2019-06-03 | soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode() | Nico Huber |
| 2019-05-29 | src/soc: Add missing 'include <types.h>' | Elyes HAOUAS |
| 2019-05-28 | soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware | Bora Guvendik |
| 2019-05-22 | post_code: add post code for hardware initialization failure | Keith Short |
| 2019-05-22 | soc/intel/cannonlake: Dump ME f/w version and status information | Tim Wawrzynczak |
| 2019-05-21 | soc/intel: Remove unused pointer argument in mca_configure() | Subrata Banik |
| 2019-05-20 | soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD. | Tim Wawrzynczak |
| 2019-05-20 | soc/intel/cannonlake: Make use of gpio_pm_configure() | Subrata Banik |
| 2019-05-18 | soc/intel: Fill DIMM serial number from SPD | Duncan Laurie |
| 2019-05-15 | soc/intel/cannonlake: Support different SPD read type for each slot | Philip Chen |
| 2019-05-13 | soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file | Elyes HAOUAS |
| 2019-05-11 | soc/intel/cnl: Enable VT-d | John Zhao |
| 2019-05-09 | soc/intel/cannonlake: Fix pcie clock number | Lijian Zhao |
| 2019-05-07 | mb/google/sarien: Add SMBIOS type 9 fields | Lijian Zhao |
| 2019-05-06 | soc/intel/cannonlake/acpi: Add board level s0ix call back | Eric Lai |
| 2019-05-06 | soc/intel/cannonlake: Add GPIO dual-route support. | Tim Wawrzynczak |
| 2019-05-01 | mb/google/sarien: Disable S5 wake on LAN by default | Eric Lai |
| 2019-04-30 | vboot: refactor OPROM code | Joel Kitching |
| 2019-04-29 | soc/intel: Add GPI interrupt config register offset info | Karthikeyan Ramasubramanian |
| 2019-04-29 | soc/intel/cannonlake: Modify dq_map to provide for 6 entries | Paul Fagerburg |
| 2019-04-26 | soc/{amd,intel}/chip: Use local include for chip.h | Elyes HAOUAS |
| 2019-04-25 | 3rdparty/fsp: Update submodule pointer to upstream master | Matt DeVillier |
| 2019-04-23 | soc/intel/cannonlake: add missing console.h include | Patrick Georgi |
| 2019-04-23 | soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig | Kane Chen |
| 2019-04-23 | soc/intel/cannonlake: Add null reference check for Cnvi and Xdci | Aamir Bohra |
| 2019-04-23 | src: include <assert.h> when appropriate | Elyes HAOUAS |
| 2019-04-23 | src: Add missing include 'console.h' | Elyes HAOUAS |
| 2019-04-22 | Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" | Lijian Zhao |
| 2019-04-19 | soc/intel/cannonlake: Add report for iGD 0x3ea1 | Lijian Zhao |
| 2019-04-18 | soc/intel/cnl: Generate DMAR ACPI table | John Zhao |
| 2019-04-16 | soc/intel/cannonlake: Configure Vmx support using Kconfig | Ronak Kanabar |
| 2019-04-16 | soc/intel/cannonlake: Implement soc side VMX support | Ronak Kanabar |
| 2019-04-16 | soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML | Subrata Banik |
| 2019-04-13 | soc/intel/cpulib: Remove redundent enable/disable functions | Subrata Banik |
| 2019-04-12 | soc/intel/cannonlake: Select FSP_M_XIP | Furquan Shaikh |
| 2019-04-12 | soc/intel/cannonlake: Do not use XIP_ROM_SIZE | Furquan Shaikh |
| 2019-04-11 | soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups | Aamir Bohra |
| 2019-04-08 | Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() | Nico Huber |
| 2019-04-08 | src/soc/intel/cannonlake: Remove ITSS IPC restore | Aamir Bohra |
| 2019-04-06 | src: Use include <delay.h> when appropriate | Elyes HAOUAS |
| 2019-04-06 | src: Use #include <timer.h> when appropriate | Elyes HAOUAS |
| 2019-04-01 | soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree | Krishna Prasad Bhat |
| 2019-03-29 | soc/intel/cannonlake: Ignore GBE LTR | Lijian Zhao |
| 2019-03-28 | soc/intel/cannonlake: Update CPU Ratio base on MSR | Lijian Zhao |
| 2019-03-27 | soc/intel/cannonlake: Configure voltage margining policies | Krzysztof Sywula |
| 2019-03-25 | soc/intel/cannonlake: Clear PMCON status bits | Krishna Prasad Bhat |
| 2019-03-24 | soc/intel/common: Remove common chip config use_fsp_mp_init | Subrata Banik |
