summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake
AgeCommit message (Expand)Author
2017-12-09soc/intel/cannonlake: Clean up UART codeAamir Bohra
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
2017-12-07soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik
2017-12-05soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh
2017-12-02soc/intel/cannonlake: Initialize PMC controllerSubrata Banik
2017-11-23soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar
2017-11-23soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to resetJohn Zhao
2017-11-20soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao
2017-11-17soc/intel/cannonlake: fix gpio pin numbersBora Guvendik
2017-11-17soc/intel/cannonlake: Add cpu.asl fileShaunak Saha
2017-11-15soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar
2017-11-13soc/intel/cannonlake: Define default LPSS clockLijian Zhao
2017-11-11soc/intel/cannonlake: Make use of Intel SPI common blockSubrata Banik
2017-11-11soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik
2017-11-10soc/intel/cannonlake: Remove structure variable initialization with 0Subrata Banik
2017-11-04soc/intel/cannonlake: Add DSP supportLijian Zhao
2017-11-04soc/intel/cannonlake: Install common i2cLijian Zhao
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
2017-11-01soc/intel/cannonlake: Use SCS common codeBora Guvendik
2017-10-27soc/intel/cannonlake: Use common p2sb driverLijian Zhao
2017-10-26soc/intel/cannonlake: Add support for C state and P stateShaunak Saha
2017-10-26soc/intel/cannonlake: remove duplicate power_state migrationPatrick Georgi
2017-10-23soc/intel/cannonlake: Increase stack size from 4KiB to 8KiBJohn Zhao
2017-10-22soc/intel/cannonlake: Change max root port to 16Lijian Zhao
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
2017-10-20soc/intel/cannonlake: Add platform.aslLijian Zhao
2017-10-19soc/intel/cannonlake: Fix HECI error on resetLijian Zhao
2017-10-19soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik
2017-10-19soc/intel/cannonlake: Add IGD Support and pre-OS display codeAbhay Kumar
2017-10-18soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao
2017-10-18soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao
2017-10-18soc/intel/cannonlake: Add finalize functionLijian Zhao
2017-10-18soc/intel/cannonlake: Calculate soc reserved memory sizeSubrata Banik
2017-10-18soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik
2017-10-18soc/intel/cannonlake: Refactor memory layout calculationSubrata Banik
2017-10-18soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik
2017-10-12soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh
2017-10-12soc/intel/cannonlake: add length information for communitiesBora Guvendik
2017-10-12soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar
2017-10-11soc/intel/cannonlake: Change default UART number to 2Lijian Zhao
2017-10-09soc/intel/*lake: Load vbt when it's neededPatrick Georgi
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
2017-10-06soc/intel/cannonlake: Enable MRC cacheLijian Zhao
2017-10-06soc/intel/cannonlake: reduce bootblock sizeAaron Durbin
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
2017-10-03soc/intel/cannonlake: change gpio device nameBora Guvendik
2017-10-03soc/intel/cannonlake: Disable CPU ratio overrideLijian Zhao
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
2017-10-03soc/intel/cannonlake: Add lpc pci driverLijian Zhao
2017-09-27soc/intel/cannonlake: Add FSP GOP supportAbhay kumar
2017-09-21soc/intel/cannonlake: Remove old soc_get_rtc_failed functionMartin Roth
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
2017-09-20soc/intel/cannonlake: add rtc failure checkingAaron Durbin
2017-09-20soc/intel/cannonlake: Add PMC pci driversLijian Zhao
2017-09-19soc/intel/cannonlake: Add PCIE IRQsBora Guvendik
2017-09-14src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
2017-09-13soc/intel/cannonlake: Add serialio device configLijian Zhao
2017-09-13soc/intel/cannonlake: Add ramstage uart debug supportLijian Zhao
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
2017-09-11cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin
2017-09-06soc/intel/cannonlake: remove duplicate uart.c from bootblockNick Vaccaro
2017-09-06soc/intel/cannonlake: Add Vboot/ChromeOS supportLijian Zhao
2017-09-06soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocworkSubrata Banik
2017-09-05soc/intel/cannonlake: Set IGD stolen memory size to 64MBSubrata Banik
2017-09-02soc/intel/cannonlake: Use common mca_configure() APIPratik Prajapati
2017-09-01soc/intel/cannonlake: Define Max PCIE Root PortsPratik Prajapati
2017-09-01soc/intel/cannonlake: add *spi.c files to makeNick Vaccaro
2017-09-01soc/intel/cannonlake: add gpio files to makeNick Vaccaro
2017-09-01soc/intel/canonlake: Enable LPSS UART in 32bit PCI modeLijian Zhao
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
2017-08-30soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik
2017-08-29soc/intel/cannonlake: Fix Coverity scan errorLijian Zhao
2017-08-26soc/intel/cannonlake: use __packedAaron Durbin
2017-08-25soc/intel/cannonlake: Init UPD params based on configPratik Prajapati
2017-08-24soc/intel/cannonlake: Add cpu.c and MP init supportPratik Prajapati
2017-08-22soc/intel/cannonlake: Define soc_intel_cannonlake_configPratik Prajapati
2017-08-21soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao
2017-08-21soc/intel/cannonlake: Add support for all UART port indexSubrata Banik
2017-08-21soc/intel/cannonlake: Add Kconfig option to select UART indexSubrata Banik
2017-08-17soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao
2017-08-17intel/cannonlake/chip: Add initial PCI enum supportPratik Prajapati
2017-08-16soc/intel/cannonlake: Add proper support to enable UART2 in 16550 modeSubrata Banik
2017-08-15soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
2017-08-15soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
2017-08-14soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik
2017-08-14soc/intel/cannonlake: Initialize struct member to 0Subrata Banik
2017-08-11soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein
2017-08-11soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh
2017-08-09soc/intel/cannonlake: Add ramstage SystemAgent supportLijian Zhao
2017-08-07soc/intel/cannonlake: Add memory map supportLijian Zhao
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
2017-07-24Update files with no newline at the endMartin Roth
2017-07-24Fix files with multiple newlines at the end.Martin Roth