coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-07-24	Update files with no newline at the end	Martin Roth
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-07-22	soc/intel/cannonlake: Keep variable from going out of scope	Martin Roth
2017-07-21	Revert "soc/intel/cannonlake: Add postcar stage support"	Martin Roth
2017-07-21	Revert "soc/intel/cannonlake: Call into FSP siliconinit"	Martin Roth
2017-07-21	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-07-21	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-07-20	soc/intel/cannonlake: Make ramstage relocatable	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add microcode support	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Fix Build break	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Use common GPIO driver	Andrey Petrov
2017-07-18	soc/intel/cannonlake: Add PMC headers	Andrey Petrov
2017-07-17	soc/intel/cannonlake: remove top_of_32bit_ram() declaration	Aaron Durbin
2017-07-13	soc/intel/cannonlake: Add reset.c	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add Makefile	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add bootblock PCH	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add early CPU initialization	Andrey Petrov
2017-07-12	soc/intel/cannonlake: Add PCI dev macros and IDs	Andrey Petrov
2017-07-12	soc/intel/cannonlake: Add report_platform.c	Andrey Petrov
2017-07-02	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add UART initialization	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add initial dummy directory	Lijian Zhao