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Change-Id: Ia951a466479b1e98e49895705162a66aece7609b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.
Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add Cannon Lake SoC boilerplate directory with:
* SoC directory
* Base Kconfig
* Dummy cbmem.c
Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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