coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-06-03	soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode()	Nico Huber
	This is never called: The only calling path is guarded by both !DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. If somebody figures out how this is supposed to be used, we can easily revive the implementation. Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23	src: include <assert.h> when appropriate	Elyes HAOUAS
	Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
	Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-20	src: Use 'include <string.h>' when appropriate	Elyes HAOUAS
	Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
	This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-14	src: Get rid of device_t	Elyes HAOUAS
	Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-14	soc/intel/cannonlake: Fix UART2 serial log broken issue	Subrata Banik
	Cannonlake rvp serial log has been regressed with commit I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake: Clean up UART code) because of common UART code is unable to link all __weak function implementation from SoC uart.c due to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI device resource programming is different than what it's been programmed before. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected. Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09	soc/intel/cannonlake: Clean up UART code	Aamir Bohra
	Clean up and move UART related code under a single uart.c file. Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-21	soc/intel/cannonlake: Add support for all UART port index	Subrata Banik
	Select LPSS UART Base address based on LPSS UART port index. Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-16	soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode	Subrata Banik
	Need to perform a dummy read in order to activate LPSS UART's 16550 8-bit compatibility mode. TEST=Able to get serial log in both 32 bit and 8 bit mode through LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and CONFIG_DRIVERS_UART_8250MEM selection. Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
	Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21	Revert "soc/intel/cannonlake: Add postcar stage support"	Martin Roth
	This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
	Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29	soc/intel/cannonlake: Add UART initialization	Andrey Petrov
	Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>