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Age
Commit message (
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Author
2018-04-24
compiler.h: add __weak macro
Aaron Durbin
2018-04-19
soc/intel/cannonlake: Set DISB after Dram init
Lijian Zhao
2018-04-05
soc/intel/cannonlake: Add VT-d and VMX programming
Lijian Zhao
2018-02-14
intel/fsp: Update cannonlake fsp header
Lijian Zhao
2018-02-08
soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
Subrata Banik
2018-01-25
soc/intel/cannonlake: enable pch link in bootblock
Caveh Jalali
2018-01-16
soc/intel/cannonlake: Program DMI PCR settings
Lijian Zhao
2017-12-20
soc/intel/cannonlake: Tell FSPM UART port number
Lijian Zhao
2017-10-19
soc/intel/cannonlake: Fix HECI error on reset
Lijian Zhao
2017-10-18
soc/intel/cannonlake: Set platform Debug Probe Type
Lijian Zhao
2017-10-03
soc/intel/cannonlake: Disable CPU ratio override
Lijian Zhao
2017-09-05
soc/intel/cannonlake: Set IGD stolen memory size to 64MB
Subrata Banik
2017-09-01
soc/intel/cannonlake: Define Max PCIE Root Ports
Pratik Prajapati
2017-08-30
soc/intel/cannonlake: Add PrmrrSize and C6DRAM config
Subrata Banik
2017-08-25
soc/intel/cannonlake: Init UPD params based on config
Pratik Prajapati
2017-08-21
soc/intel/cannonlake: Enable common PMC code for CNL
Lijian Zhao
2017-08-15
soc/intel/cannonlake: Add postcar stage support
Lijian Zhao
2017-07-24
Update files with no newline at the end
Martin Roth
2017-07-21
Revert "soc/intel/cannonlake: Add postcar stage support"
Martin Roth
2017-07-21
soc/intel/cannonlake: Add postcar stage support
Lijian Zhao
2017-07-19
soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit
Lijian Zhao