| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-07-21 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
| 2017-07-19 | soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit | Lijian Zhao |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |