Age | Commit message (Expand) | Author |
---|---|---|
2017-10-19 | soc/intel/cannonlake: Fix HECI error on reset | Lijian Zhao |
2017-10-18 | soc/intel/cannonlake: Set platform Debug Probe Type | Lijian Zhao |
2017-10-03 | soc/intel/cannonlake: Disable CPU ratio override | Lijian Zhao |
2017-09-05 | soc/intel/cannonlake: Set IGD stolen memory size to 64MB | Subrata Banik |
2017-09-01 | soc/intel/cannonlake: Define Max PCIE Root Ports | Pratik Prajapati |
2017-08-30 | soc/intel/cannonlake: Add PrmrrSize and C6DRAM config | Subrata Banik |
2017-08-25 | soc/intel/cannonlake: Init UPD params based on config | Pratik Prajapati |
2017-08-21 | soc/intel/cannonlake: Enable common PMC code for CNL | Lijian Zhao |
2017-08-15 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
2017-07-24 | Update files with no newline at the end | Martin Roth |
2017-07-21 | Revert "soc/intel/cannonlake: Add postcar stage support" | Martin Roth |
2017-07-21 | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao |
2017-07-19 | soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit | Lijian Zhao |