coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-11-16	src: Remove unneeded include <cbmem.h>	Elyes HAOUAS
	Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04	soc/intel/common: add acpi_get_sleep_type to pmclib	Bora Guvendik
	Change-Id: I3f4123657a375211f802a7d484a15353f9a256e9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2017-10-26	soc/intel/cannonlake: remove duplicate power_state migration	Patrick Georgi
	Common PMC code comes with its own. Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18	soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep state	Subrata Banik
	This patch uses PMC common function to get previous sleep state using cbmem or chipset_power_state global structure. acpi_get_sleep_type is needed in PRE_RAM stage when soc selects CONFIG_EARLY_EBDA_INIT kconfig option. Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
	This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
	Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-19	soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit	Lijian Zhao
	The following minimal changes are needed to make system boot until FSP memoryinit got called. 1. Program SA BARs 2. Assume previous power state is S0. Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>