coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-12-02	soc/intel/cannonlake: Initialize PMC controller	Subrata Banik
	PMC controller gets hidden during FSP-Silicon initialization using sideband interface on CannonLake platform. Hence accessing PWRMBASE using PCI config space will return invalid BAR value as 0xFFFFF000. Also PMC PCI driver will not be able to initialize PMC controller as its not showing over PCI bus. coreboot PCI enumeration log shows: PCI: Static device PCI: 00:1f.2 not found, disabling it. This patch ensures PMC controller is getting initialized using boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/ BS_ON_EXIT). TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT. Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-22	security/vboot: Move vboot2 to security kconfig section	Philipp Deppenwiese
	This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-12	soc/intel/common: Clean up PMC library GPE handling API	Furquan Shaikh
	1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20	vboot: reset vbnv in cmos when cmos failure occurs	Aaron Durbin
	There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20	soc/intel/cannonlake: add rtc failure checking	Aaron Durbin
	In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. In addition actually provide soc_get_rtc_failed() which properly indicates to the common code that RTC failure did occur in the cmos_init() path. BUG=b:63054105 Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13	soc/intel/cannonlake: Add common ACPI support for CNL	Lijian Zhao
	Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-29	soc/intel/cannonlake: Fix Coverity scan error	Lijian Zhao
	Add return in case of null pointer to avoid coverity scan error, fixed 1.Coverity ID 1379849: Null pointer dereferences (FORWARD_NULL) 2.Coverity ID 1379848: Null pointer dereferences (FORWARD_NULL) Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
	This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>