coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-10-03	soc/intel/cannonlake: Fill the SMI usage	Lijian Zhao
	Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06	soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocwork	Subrata Banik
	This patch fixes klocwork bug due to recent memmap.c implementation where “Pointer 'dev' returned from call to function 'dev_find_slot' at line 144 may be NULL.” Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-01	soc/intel/cannonlake: Perform dram top calculation based on HW registers	Subrata Banik
	This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao
	Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>