coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-05-22	post_code: add post code for hardware initialization failure	Keith Short
2019-04-26	soc/{amd,intel}/chip: Use local include for chip.h	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2018-06-22	soc/intel/cannonlake: Remove DMA support for PTT	Subrata Banik
2018-04-11	soc/intel: Remove superfluous pointers variables	Arthur Heymans
2017-10-19	soc/intel/cannonlake: Use EBDA structure to store soc reserve memory size	Subrata Banik
2017-10-18	soc/intel/cannonlake: Calculate soc reserved memory size	Subrata Banik
2017-10-18	soc/intel/cannonlake: Use EBDA area to store cbmem_top address	Subrata Banik
2017-10-18	soc/intel/cannonlake: Refactor memory layout calculation	Subrata Banik
2017-10-03	soc/intel/cannonlake: Fill the SMI usage	Lijian Zhao
2017-09-06	soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocwork	Subrata Banik
2017-09-01	soc/intel/cannonlake: Perform dram top calculation based on HW registers	Subrata Banik
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao