coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-01-17	soc/intel/cannonlake: Reserve PMC IO resources	Subrata Banik
	PMC controller gets hidden during FSP Silicon initialization using sideband interface on CNP-PCH. Hence unable to reserve PMC IO resources during PCI enumeration process. This causes hang issue on non-chrome platform with CNP-PCH due to ABASE corruption. This patch ensures PMC IO resource (ABASE) is getting reserved (IO address 0x1800-0x1900) and ACPI base is not overwritten by other devices. TEST=ABASE range is reserved along with LPC IO range during PCI enumeration. PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17	soc/intel/common: Add option to pass SoC IO resource	Subrata Banik
	This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16	soc/intel/cannonlake: Program DMI PCR settings	Lijian Zhao
	According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03	soc/intel/cannonlake: Add lpc pci driver	Lijian Zhao
	1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>