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path: root/src/soc/intel/cannonlake/include
AgeCommit message (Expand)Author
2019-02-15soc/intel/cannonlake: Define VR settingsRoy Mingi Park
2019-02-07soc/intel/cannonlake: Configure GPIOs again after FSP-S is doneFurquan Shaikh
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
2019-01-16soc/intel/cannonlake: Add processor power limits control supportSumeet Pawnikar
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
2019-01-09soc/intel/cannonlake: Enable/Disable IPU based on devicetree switchV Sowmya
2019-01-08soc/intel/cannonlake: Add chipset event loggingDuncan Laurie
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
2018-12-19soc/intel/cannonlake: Amend comment typoLijian Zhao
2018-12-14soc/intel/cannonlake: Fix CNL-H GPIO pin mapDuncan Laurie
2018-11-27soc/intel/cannonlake: Delete unused macros in lpc.hSubrata Banik
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-26soc/intel/cannonlake: Add back PM TIMER EMULATIONLijian Zhao
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
2018-10-09soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-04src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS
2018-09-21soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh
2018-09-20soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
2018-06-22soc/intel/cannonlake: Remove DMA support for PTTSubrata Banik
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
2018-02-22soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao
2018-02-22soc/intel/cannonlake: Add provision to make CSME function disable in SMM modeSubrata Banik
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
2018-02-16soc/intel/cannonlake: Add missing GPIO pin definitionsLijian Zhao
2018-02-11soc/intel/cannonlake: Add Pch iSCLK programmingLijian Zhao
2018-01-23src/soc/intel/cannonlake: Update C-state latency control limitsVaibhav Shankar
2018-01-23mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya
2018-01-23soc/intel/cannonlake: Add audio NHLT supportLijian Zhao
2018-01-09soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik
2018-01-07soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro
2018-01-05soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
2017-12-11soc/intel/cannonlake: Add support for D0 steppingLijian Zhao
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
2017-12-05soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh
2017-11-17soc/intel/cannonlake: fix gpio pin numbersBora Guvendik
2017-11-11soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
2017-10-27soc/intel/cannonlake: Use common p2sb driverLijian Zhao
2017-10-26soc/intel/cannonlake: Add support for C state and P stateShaunak Saha
2017-10-19soc/intel/cannonlake: Fix HECI error on resetLijian Zhao
2017-10-19soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik
2017-10-18soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao
2017-10-18soc/intel/cannonlake: Add finalize functionLijian Zhao
2017-10-18soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik
2017-10-03soc/intel/cannonlake: change gpio device nameBora Guvendik
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
2017-10-03soc/intel/cannonlake: Add lpc pci driverLijian Zhao
2017-09-20soc/intel/cannonlake: Add PMC pci driversLijian Zhao
2017-09-14src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati
2017-09-13soc/intel/cannonlake: Add serialio device configLijian Zhao
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
2017-08-26soc/intel/cannonlake: use __packedAaron Durbin
2017-08-25soc/intel/cannonlake: Init UPD params based on configPratik Prajapati
2017-08-22soc/intel/cannonlake: Define soc_intel_cannonlake_configPratik Prajapati
2017-08-21soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao
2017-08-21soc/intel/cannonlake: Add support for all UART port indexSubrata Banik
2017-08-17soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao
2017-08-15soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
2017-08-15soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
2017-08-14soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik
2017-08-11soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein
2017-08-11soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh
2017-08-07soc/intel/cannonlake: Add memory map supportLijian Zhao
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
2017-07-24Fix files with multiple newlines at the end.Martin Roth
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-07-19soc/intel/cannonlake: Add minimal changes to call FSP MemoryinitLijian Zhao
2017-07-18soc/intel/cannonlake: Fix Build breakLijian Zhao
2017-07-18soc/intel/cannonlake: Use common GPIO driverAndrey Petrov
2017-07-18soc/intel/cannonlake: Add PMC headersAndrey Petrov
2017-07-17soc/intel/cannonlake: remove top_of_32bit_ram() declarationAaron Durbin
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov