coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/cannonlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-01-10	soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper	Subrata Banik
2019-10-21	Revert "soc/intel/cannonlake: Remove DMA support for PTT"	Jeremy Soller
2019-06-03	soc/intel: Replace UART_BASE() and friends with a Kconfig	Nico Huber
2019-04-18	soc/intel/cnl: Generate DMAR ACPI table	John Zhao
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
2018-06-22	soc/intel/cannonlake: Remove DMA support for PTT	Subrata Banik
2017-10-27	soc/intel/cannonlake: Use common p2sb driver	Lijian Zhao
2017-10-19	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao
2017-10-03	soc/intel/cannonlake: Add northbridge dsdt table	Lijian Zhao
2017-09-01	soc/intel/cannonlake: Perform dram top calculation based on HW registers	Subrata Banik
2017-08-21	soc/intel/cannonlake: Add support for all UART port index	Subrata Banik
2017-07-02	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov