coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-04	soc/intel/{skl,cnl}: add NMI_{EN,STS} registers	Michael Niewöhner
2020-09-17	soc/intel/cannonlake: add missing special function pads	Michael Niewöhner
2020-09-17	soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names	Michael Niewöhner
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-05-20	soc/intel/cannonlake: Make use of gpio_pm_configure()	Subrata Banik
2019-04-29	soc/intel: Add GPI interrupt config register offset info	Karthikeyan Ramasubramanian
2019-02-26	soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO	Rizwan Qureshi
2018-12-14	soc/intel/cannonlake: Fix CNL-H GPIO pin map	Duncan Laurie
2018-10-17	soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions	praveen hodagatta pranesh