| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-01-14 | soc/intel/cannonlake: Provide interface to update TCC offset | John Su |
| 2019-01-08 | soc/intel/cannonlake: Add FSP UPD for minimum assertion width | Duncan Laurie |
| 2019-01-01 | soc/intel/cannonlake: Enable CNVi based on devicetree | Maulik V Vaghela |
| 2018-12-19 | soc/intel/cannonlake: SATA and DMI power optimize | Lijian Zhao |
| 2018-12-19 | soc/intel/cannonlake: Add Acoustic features | Lijian Zhao |
| 2018-11-17 | soc/intel/cannonlake: Add options for pcie ltr | Lijian Zhao |
| 2018-11-05 | soc/intel/cannonlake: Remove depreciated UPD selection | Lijian Zhao |
| 2018-10-09 | soc/intel/cannonlake: Disable Legacy PME for Root ports | Subrata Banik |
| 2018-10-08 | Move compiler.h to commonlib | Nico Huber |
| 2018-10-04 | soc/intel/cannonlake: Move the FSP related callbacks to separate files | Rizwan Qureshi |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |