coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-07-31	soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix	Sumeet Pawnikar
	Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21	soc/intel: Fix chip_info for PCH_DEV_PMC	Kyösti Mälkki
	Since PCH_DEVFN_PMC device is a PCI device that may be hidden from enumeration, use SA_DEVFN_ROOT instead to locate the SOC configuration. Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07	soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC	Furquan Shaikh
	PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 TEST=Verified that S3 works fine on hatch. Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-28	soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware	Bora Guvendik
	Dumping ME status displays wrong information if we disable Heci1 because it is called after fsp notifies EndOfFirmware and disables Heci1. This patch moves the ME status dump before fsp notify EndOfFirmware. TEST=Boot to OS, check ME dump information Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-22	soc/intel/cannonlake: Dump ME f/w version and status information	Tim Wawrzynczak
	At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints seemingly sane values on WHL and CML devices. Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-26	soc/{amd,intel}/chip: Use local include for chip.h	Elyes HAOUAS
	Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25	soc/intel/cannonlake: Clear PMCON status bits	Krishna Prasad Bhat
	The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. BUG=b:128482282 BRANCH=None TEST=In cbmem logs, check for value of “prev_sleep_state” using command cbmem –c \| grep “prev_sleep_state” For cold reboot, "prev_sleep_state 5" For warm reboot, "prev_sleep_state 0" Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
	MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10	soc/intel/common/block: Move tco common functions into block/smbus	Subrata Banik
	This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-01	soc/intel/cannonlake: Get rid of device_t	Elyes HAOUAS
	Use of device_t has been abandoned in ramstage. Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26584 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22	soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode	Subrata Banik
	TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11	soc/intel/cannonlake: Add Pch iSCLK programming	Lijian Zhao
	In order to reduce BOM cost and board area for imaging solution, the sensor requires a 19.2/24MHz reference clock from PCH. In addition to that, having PCH to supply the sensor reference clock will prevent dependency on CPU power management and also avoid level shifter cost. Pch iSCLK is only required for CNP-LP with the camera sensor on the platform. BUG=None TEST=Boot up into OS and read back PCH iSCLK programming through iotools. Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23367 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18	soc/intel/cannonlake: Add finalize function	Lijian Zhao
	Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>