coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-12-05	soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENT	Furquan Shaikh
	DSX_CFG provides a config option to disable internal pull-down on AC_PRESENT. This change updates macro name to reflect this correctly. Change-Id: I620d7da4048178f86de41f3afd98543cf8efc5ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04	soc/intel/cannonlake: Install common i2c	Lijian Zhao
	Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-01	soc/intel/cannonlake: Use SCS common code	Bora Guvendik
	This patch uses common SCS library to set up sd card. Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18	soc/intel/cannonlake: Set platform Debug Probe Type	Lijian Zhao
	Add option for user to select what kind of probe can be used for platform debug. TEST=Set to XDP and boot up system with XDP hooked, able to halt. Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21942 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18	soc/intel/cannonlake: Update PCIE CLKREQ programing	Lijian Zhao
	UPD of PCI express clock request was updated in FSP 7.0.14.11, change that in coreboot accordingly. TEST=NONE Change-Id: I2261deccfb489c0de577d580997744a484f07a04 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03	soc/intel/cannonlake: Add lpc pci driver	Lijian Zhao
	1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20	soc/intel/cannonlake: Add PMC pci drivers	Lijian Zhao
	Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13	soc/intel/cannonlake: Add serialio device config	Lijian Zhao
	Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13	soc/intel/cannonlake: Add common ACPI support for CNL	Lijian Zhao
	Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30	soc/intel/cannonlake: Add PrmrrSize and C6DRAM config	Subrata Banik
	This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25	soc/intel/cannonlake: Init UPD params based on config	Pratik Prajapati
	Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21175 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-22	soc/intel/cannonlake: Define soc_intel_cannonlake_config	Pratik Prajapati
	- Populate soc_intel_cannonlake_config - Add usb.h and vr_config.h for CannonLake Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
	This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17	soc/intel/cannonlake: Add SPI flash controller driver	Lijian Zhao
	Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
	The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. This patch was merged too early, and reverted. Originally reviewed on https://review.coreboot.org/#/c/20581 Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20687 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21	Revert "soc/intel/cannonlake: Call into FSP siliconinit"	Martin Roth
	This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
	The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>