coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-01-26	soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and report	Lijian Zhao
2018-01-25	soc/intel/cannonlake: enable pch link in bootblock	Caveh Jalali
2018-01-16	soc/intel/cannonlake: Program DMI PCR settings	Lijian Zhao
2018-01-10	soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock	Furquan Shaikh
2018-01-09	soc/intel/cannonlake: Remove redundent CNL CPUID macros	Subrata Banik
2018-01-05	soc/intel/cannonlake: Correct PMC/GPIO routing information	Lijian Zhao
2017-12-08	soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c	Subrata Banik
2017-10-19	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao
2017-10-18	soc/intel/cannonlake: Use EBDA area to store cbmem_top address	Subrata Banik
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-07-22	soc/intel/cannonlake: Keep variable from going out of scope	Martin Roth
2017-07-18	soc/intel/cannonlake: Fix Build break	Lijian Zhao
2017-07-13	soc/intel/cannonlake: Add bootblock PCH	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add early CPU initialization	Andrey Petrov
2017-07-12	soc/intel/cannonlake: Add report_platform.c	Andrey Petrov
2017-07-02	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov