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path: root/src/soc/intel/cannonlake/bootblock/report_platform.c
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2019-08-28soc/intel/cnl: Add CML IGD IDsMeera Ravindranath
BUG=b:139798422 TEST=Build and boot CMLRVP. Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-16soc/intel/cannonlake: Add more PCI Ids for CoffeelakeChristian Walter
Change-Id: I92e2adb32d19ff49bdef353e1f191c4960ce0d18 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-12soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics idNico Huber
Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12soc/intel/common: Add CM246 LPC device idNico Huber
Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19soc/intel/cannonlake: Add report for iGD 0x3ea1Lijian Zhao
Integrated graphics id 0x3ea1 reported as unknown in bootblock stage, make it correct. BUG=N/A TEST=Boot up into sarien platform and check with serial log, it shows IGD: device id 3ea1 (rev 02) is Whiskeylake ULT GT1. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I2c4c697b108be7fa74736514ca71469a1ca29c22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-28soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik
This patch adds CML-U 2+2 SA DID into systemagent.c and report platform. Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31638 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/intel/common: Include cometlake PCH IDsRonak Kanabar
Add cometlake specific PCH IDs Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-24soc/intel/common: Include cometlake SA IDsRonak Kanabar
Add cometlake specific SA IDs Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24soc/intel/common: Include cometlake CPU IDsRonak Kanabar
Add cometlake specific CPU IDs Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-23soc/intel/cannonlake: Make few more whitespace proper in MCH nameSubrata Banik
CB:31547 fixes few whitespace error. Here is few more whitespace clean up. Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-22soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD nameSubrata Banik
Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-19soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Reviewed-on: https://review.coreboot.org/c/31433 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20soc/intel/common/block: Add WHL 2-core SKUKrzysztof Sywula
There are two SKUs of Whiskey Lake W0, 2-core and 4-core. Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-10src/soc/intel: Add new device IDs to support coffeelakeMaulik
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-03soc/intel/cannonlake: Report Whiskey Lake infoLijian Zhao
According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized. Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-26soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and reportLijian Zhao
Both early platform information reporting in bootblock and common code CPU driver will add support for cannonlake D0 stepping processor. BUG=None TEST=Boot up system with D0 stepping CPU installed, check serial log that can display as D0 stepping. Change-Id: I76ee974ee027100d7853a110f95b1601987492e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-09soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik
This patch ensures all CannonLake CPUIDs are part of mp_init.h hence remove duplicate macro definitions from SoC code. TEST=Build and boot CannonLake RVP Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision are available in single stage and makes use of local references. TEST=Build and boot cannonlake_rvp to get PCH information as below PCH: device id xxxx (rev xx) is Cannonlake-Y Premium Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
The variable p was going out of scope while still being pointed to by *cpu_name. Fix coverity ID 1378215 (Pointer to local outside scope) Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
Dump basic platform information early in bootblock. Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20068 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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