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path: root/src/soc/intel/cannonlake/bootblock/bootblock.c
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2019-12-26soc/intel/cannonlake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-02soc/intel/cannonlake: Fix compilationPraveen Hodagatta Pranesh
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-TSubrata Banik
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-01soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09soc/intel: Clean mess around UART_DEBUGNico Huber
Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-03soc/intel/cannonlake: Load FSP teardown optionallyLijian Zhao
Make build still pass in case of no FsptUpd.h available. BUG=N/A TEST=Delete FsptUpd.h and build pass wihtout FSP_CAR set. Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-10-25soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-18soc/intel/cannonlake: Fix Build breakLijian Zhao
1.Replace outdated defination of TCO_EN to TCO_BASE_EN 2.Remove setmaxfreq() as not needed any more. Change-Id: Id54fdfd14f1abaa592132195e6f9acfa5807626e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
Change-Id: Ia951a466479b1e98e49895705162a66aece7609b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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