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path: root/src/soc/intel/cannonlake/acpi
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2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23soc/intel/cannonlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: I3b85fec3de8f33d338425a417cc8b0f5290a5e4f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78520 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-09mb/prodrive/hermes: Hook up wake on USB optionAngel Pons
Hook up the `wake_on_usb` EEPROM setting so that it works as intended. TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3. Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/cannonlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I349a2b24ecdee347548b5c7b292c5075e6150a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72033 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b)` with `a << b`. Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/cannonlake/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: Ib00f363b48295ed1c000a839f54d5ea5dc2b88e2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I12c855437a581beade2d218b8f710cf1b32cb841 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Ic9836acb4d32f2ce30c3c6d488bc22ddc64bf365 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-01-01soc/intel/cannonlake/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b)` with `a * b`. Change-Id: I6dc9f57773754e89df4b4ffd088a4693af0452e3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31soc/intel/cannonlake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I90dc0ecb1e3f16874a72cdf01afb097d4e7b6076 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60503 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-31soc/intel/cannonlake/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: Ibc5aeb5e8d85556d7564033ec92deb5b2dae093d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30soc/intel/cannonlake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I764bf6c8b068c1b7471a28aa064f7a3a47d7811e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30soc/intel/cannonlake/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I259bd218ac3f786cef6e05386f6dc55ccaf6b911 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60468 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10soc/intel/cannonlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch cannonlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-29soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows cannonlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. Also prodrive/hermes (intel/cannonlake) was the only user of uart_acpi_write_irq(), therefore use the allocated IRQ instead of the fixed IRQ number in that function to preserve behavior. BUG=b:130217151 TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 11 0 0 0 IO-APIC 2-edge timer 1: 0 661 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 874 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 1 0 IO-APIC 14-fasteoi INT34BB:00 17: 0 10633 0 0 IO-APIC 17-fasteoi mmc1 19: 0 0 0 0 IO-APIC 19-fasteoi mmc0 22: 0 0 0 0 IO-APIC 22-fasteoi i801_smbus 26: 153738 0 0 0 IO-APIC 26-fasteoi idma64.0, i2c_designwar 27: 0 8 0 0 IO-APIC 27-fasteoi idma64.1, i2c_designwar 30: 0 0 227 0 IO-APIC 30-fasteoi i2c_designware.2 33: 0 0 0 0 IO-APIC 33-fasteoi idma64.3 35: 43107 0 0 0 IO-APIC 35-fasteoi idma64.4, pxa2xx-spi.4 36: 0 0 2039 0 IO-APIC 36-fasteoi idma64.5, pxa2xx-spi.5 45: 0 0 9451 0 IO-APIC 45-edge ELAN0000:00 85: 0 0 0 0 IO-APIC 85-fasteoi chromeos-ec 93: 0 7741 0 0 IO-APIC 93-edge cr50_spi abbreviated _PRT dump: If (PICM) Package () {0x0001FFFF, 0x00, 0x00, 0x10}, Package () {0x0001FFFF, 0x01, 0x00, 0x11}, Package () {0x0001FFFF, 0x02, 0x00, 0x12}, Package () {0x0002FFFF, 0x00, 0x00, 0x13}, Package () {0x0004FFFF, 0x00, 0x00, 0x14}, Package () {0x0005FFFF, 0x00, 0x00, 0x15}, Package () {0x0008FFFF, 0x00, 0x00, 0x16}, Package () {0x0012FFFF, 0x01, 0x00, 0x17}, Package () {0x0012FFFF, 0x02, 0x00, 0x10}, Package () {0x0012FFFF, 0x00, 0x00, 0x18}, Package () {0x0013FFFF, 0x00, 0x00, 0x19}, Package () {0x0014FFFF, 0x00, 0x00, 0x11} Package () {0x0014FFFF, 0x01, 0x00, 0x12}, Package () {0x0014FFFF, 0x02, 0x00, 0x13}, Package () {0x0014FFFF, 0x03, 0x00, 0x14}, Package () {0x0015FFFF, 0x00, 0x00, 0x1A}, Package () {0x0015FFFF, 0x01, 0x00, 0x1B}, Package () {0x0015FFFF, 0x02, 0x00, 0x1C}, Package () {0x0015FFFF, 0x03, 0x00, 0x1D}, Package () {0x0016FFFF, 0x00, 0x00, 0x15}, Package () {0x0016FFFF, 0x01, 0x00, 0x16}, Package () {0x0016FFFF, 0x02, 0x00, 0x17}, Package () {0x0016FFFF, 0x03, 0x00, 0x10}, Package () {0x0017FFFF, 0x00, 0x00, 0x11}, Package () {0x0019FFFF, 0x00, 0x00, 0x1E}, Package () {0x0019FFFF, 0x01, 0x00, 0x1F}, Package () {0x0019FFFF, 0x02, 0x00, 0x20}, Package () {0x001AFFFF, 0x00, 0x00, 0x12}, Package () {0x001CFFFF, 0x00, 0x00, 0x10}, Package () {0x001CFFFF, 0x01, 0x00, 0x11}, Package () {0x001CFFFF, 0x02, 0x00, 0x12}, Package () {0x001CFFFF, 0x03, 0x00, 0x13}, Package () {0x001DFFFF, 0x00, 0x00, 0x10}, Package () {0x001DFFFF, 0x01, 0x00, 0x11}, Package () {0x001DFFFF, 0x02, 0x00, 0x12}, Package () {0x001DFFFF, 0x03, 0x00, 0x13}, Package () {0x001EFFFF, 0x00, 0x00, 0x21}, Package () {0x001EFFFF, 0x01, 0x00, 0x22}, Package () {0x001EFFFF, 0x02, 0x00, 0x23}, Package () {0x001EFFFF, 0x03, 0x00, 0x24}, Package () {0x001FFFFF, 0x01, 0x00, 0x15}, Package () {0x001FFFFF, 0x02, 0x00, 0x16}, Package () {0x001FFFFF, 0x03, 0x00, 0x17}, Package () {0x001FFFFF, 0x00, 0x00, 0x14}, Else Package () {0x0001FFFF, 0x00, 0x00, 0x0B}, Package () {0x0001FFFF, 0x01, 0x00, 0x0A}, Package () {0x0001FFFF, 0x02, 0x00, 0x0B}, Package () {0x0002FFFF, 0x00, 0x00, 0x0B}, Package () {0x0004FFFF, 0x00, 0x00, 0x0B}, Package () {0x0005FFFF, 0x00, 0x00, 0x0B}, Package () {0x0008FFFF, 0x00, 0x00, 0x0B}, Package () {0x0012FFFF, 0x01, 0x00, 0x0B}, Package () {0x0012FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x00, 0x00, 0x0A}, Package () {0x0014FFFF, 0x01, 0x00, 0x0B}, Package () {0x0014FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x03, 0x00, 0x0B}, Package () {0x0016FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x01, 0x00, 0x0B}, Package () {0x0016FFFF, 0x02, 0x00, 0x0B}, Package () {0x0016FFFF, 0x03, 0x00, 0x0B}, Package () {0x0017FFFF, 0x00, 0x00, 0x0A}, Package () {0x001AFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x01, 0x00, 0x0A}, Package () {0x001CFFFF, 0x02, 0x00, 0x0B}, Package () {0x001CFFFF, 0x03, 0x00, 0x0B}, Package () {0x001DFFFF, 0x00, 0x00, 0x0B}, Package () {0x001DFFFF, 0x01, 0x00, 0x0A}, Package () {0x001DFFFF, 0x02, 0x00, 0x0B}, Package () {0x001DFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x02, 0x00, 0x0B}, Package () {0x001FFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x00, 0x00, 0x0B}, Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11soc/intel/cannonlake: Enable wake from USB in S4Patrick Rudolph
The xHCI controller supports waking the system from S1-S4. Thus specify that the deepest sleep state is S4 in _PRW. Tested on Prodrive/hermes. The board now wakes from S4 as well by pressing a key on the USB keyboard. Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12soc/intel/cannonlake: Align cosmetics with Ice LakeAngel Pons
By ironing out cosmetic differences between Cannon Lake and Ice Lake, comparing actual code differences using a diff tool becomes simpler. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-08soc/intel/common/block/acpi: Factor out common gfx.aslSubrata Banik
This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common ish.aslSubrata Banik
This patch moves ish.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CML platform. 1) Dump and disassemble DSDT, verify ISHB device present inside common ish.asl is still there with correct _ADR value. 2) Verify no ACPI error seen while running 'dmesg` from console. CML platform: Device (ISHB) { Name (_ADR, 0x00130000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } TGL/JSL platform: Device (ISHB) { Name (_ADR, 0x00120000) // _ADR: Address Name (_DDN, "Integrated Sensor Hub Controller") //_DDN: DOS Device Name } Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik
This patch moves smbus.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify SBUS device present inside common smbus.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik
This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik
List of changes: 1. Rename soc_pch_pirq_init() as pch_pirq_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27soc/intel/common/block/acpi: Factor out common gpio_op.aslSubrata Banik
This patch moves gpio_op.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify all methods present inside common gpio_op.asl like GRXS, GTXS etc. are still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-27soc/intel/cannonlake: Align gpio_op.asl with TGLSubrata Banik
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros. TEST=Able to build and boot CNL and CML platform. 1) Dump and disassemble DSDT, verify unified methods like GRXS, GTXS etc. are there. 2) Verify no ACPI error seen while running 'dmesg' from console. 3) abuild --timeless to ensure there are no other functional changes. Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25soc/intel: Use ASL 2.0 syntax for GPIO ASL helper functionSubrata Banik
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL. TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL. Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24soc/intel/cnl: drop lpit.asl in favor of common versionMichael Niewöhner
Drop lpit.asl from CNL and switch to the common one in the three boards currently using it. The only difference between the two is the usage on macros in common code instead of plain integer values. Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-17soc/intel/cannonlake: add missing special function padsMichael Niewöhner
The following parameters do nothing else than configuring the corresponding pads to native mode: - DdiPortEdp - DdiPort*Hpd - DdiPort*Ddc - GpioDdp* - SpiGpioAssign - I2c*GpioAssign - SerialIoUartDebugEnable - Gp*GpioAssign - Uart*GpioAssign - GpioEnableHdaLink - AudioLinkDmic* - AudioLinkSsp* - GpioEnableHdaSspMasterClock - AudioLinkSndw* - SmbAlertEnable Add the missing special function gpio pad groups for CNL, to be able to configure them via gpio.h instead having to set various FSP parameters. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17soc/intel/cannonlake: rename "RSVD" GPIOs to their correct namesMichael Niewöhner
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17soc/intel/cannonlake: fix GPIO community numbering in ACPIMichael Niewöhner
This corrects the GPIO community numbers in CNL-LP ACPI code. Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/cnl: Add ACPI support for PMC core OS driverMichael Niewöhner
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. Include the common pmc.asl added in commit 957481c. Test: PMC gets detected by Linux kernel module. Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45318 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09soc/intel/cannonlake: Add PCIe ports on PCH-HPatrick Rudolph
Fixes complains about missing INT configuration by the pciexp kernel modules. Tested with Linux 5.5 on Prodrive Hermes. Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devicesPatrick Rudolph
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and 0:19.2 can't be detected using standard PCI probing. Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms that advertise its PCI conformance by the _ADR attribute. Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-30soc/intel/cannonlake: Add UWES ASL into xhci.aslEdward O'Callaghan
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:159187889 BRANCH=none TEST=none Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel: remove unused dptf.asl file and other definesSumeet R Pawnikar
Remove unused cannonlake dptf.asl file and cleanup defines from apollolake dptf.asl file as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-14soc/intel/cannonlake/acpi: Capitalize hex number to unify with SkylakePaul Menzel
diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl --- src/soc/intel/skylake/acpi/pch_hda.asl 2020-05-12 11:17:42.780293920 +0200 +++ src/soc/intel/cannonlake/acpi/pch_hda.asl 2020-05-12 11:17:42.756294169 +0200 @@ -4,7 +4,7 @@ Device (HDAS) { - Name (_ADR, 0x001F0003) + Name (_ADR, 0x001f0003) Name (_DDN, "Audio Controller") Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI deviceKane Chen
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD. This commit provides _DSM method for driver to query driving strength. TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4 BUG=b:154159888 Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-09soc/intel: Remove unneeded whitespacesElyes HAOUAS
Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-06soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I48422453735d50eb9292f39a3c031073d647a17c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-14soc/intel/cannonlake: Fix ASL compilation remarksSubrata Banik
This patch fixes below ASL compilation remarks 1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL codeSubrata Banik
List of changes in this patch 1. Remove unused variables 2. Make use of absolute path 3. Define macros and use inside SA ASL 4. Rearrange code in nothbridge.asl to move MCRS object under _CRS Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-17soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash rangeWim Vervoorn
The base address of the 16 MB flash range was reported as 0xFFF00000 this causes the range to extend above the 4GB boundary. Change the base to 0xFF000000 as is the case with e.g. Skylake. BUG=N/A TEST=build Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-02soc/intel/cannonlake: Add gfx.asl fileMathew King
Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-01soc/intel/{cnl,icl,skl}: Move ipu.asl into common/block/acpiSubrata Banik
This patch creates a common instance of ipu.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer ipu.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(IMGU) presence after booting to OS. Change-Id: I4d18571008c199fd5c3dbeed8cba9374520359b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpiSubrata Banik
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/{cnl,icl,skl}: Remove unused SMI opregionSubrata Banik
TEST=Able to build and boot Hatch and DE. Change-Id: I6d63c005873fc5d67b4a44f42bb436628d7c1dc3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36462 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25soc/intel: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/intel/cannonlake: Remove unused header files from southbridge.aslAamir Bohra
Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASLTim Wawrzynczak
The GPID method returns the PCR Port ID of the given GPIO community. The CGPM method alters the given GPIO community's PM bits, given in Arg1. Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11soc/intel/cannonlake: Make EC S0ix notification optional in LPITTim Wawrzynczak
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists. Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-06-07soc/intel/cannonlake: Add _DSM method for SD controllerV Sowmya
The SD controller seems to take some time after restarting the clock at 1.8V before it actually switches from 3.3V to 1.8V. Add a _DSM method that simply sleeps when switching between 3.3V and 1.8V. Otherwise, the kernel times out too quickly waiting for the card to acknowledge the 1.8V switch. The card itself is waiting until it sees the clk signal being driven at 1.8V. BUG=b:125441242 TEST=Boot Hatch with SD card and CR2 removed, observe voltage switch succeeds. Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Signef-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06soc/intel/cannonlake/acpi: Add board level s0ix call backEric Lai
Add board level s0ix call back. Since some driver doesn't care _ON/_OFF method. Add a control method for s0ix usage. BUG=b:129177593 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04soc/intel/cnl/acpi: add ish ACPI deviceJett Rink
Create the ISH ACPI device so we can hang fields off of a _DSD table. Since this is also a PCI device that has run time probing, we can always emit the ACPI device and let the device tree turn the device on or off. BRANCH=none BUG=b:122722008 TEST=verify that _DSD table gets publish under ISH device in kernel ACPI tables. Also verified that device is still turned off if device tree for ISH is off. Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/31681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04soc/intel/cannonlake: Fix DSDT compile remarksLijian Zhao
The following remarks show up during cannonlake based platform coreboot build: dsdt.asl 55: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 136: Offset (0xa8), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Address those two remarks in coreboot. BUG=N/A TEST=Build coreboot and check build log to see no more remark. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Reviewed-on: https://review.coreboot.org/c/31666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
SD controller in CNL-PCH provides a ability to configure the behavior of SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD "SdCardPowerEnableActiveHigh" to control the same. However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power. This is because SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native function in _PS0. Hence add a Kconfig option to update the UPD, which the board can select based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround gets applied based on this config. BUG=b:123350329 Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31445 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers. BUG=b:123350329 Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC. Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
Add a function in gpio ASL library to set pad mode. BUG=b:123350329 Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-20src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix. The _DSM method gets injected into DSDT table and called from kernel. LPIT table is hardcoded in this patch but the proper way to implement is to use inject_dsdt to make the _DSM methods available for soc's to implement. Calling the LPIT table from mainboard here so that with the current implementation the platforms which do not have lpit support throw compilation error. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Reviewed-on: https://review.coreboot.org/c/31101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
Replace device name from B0D4 with TCPU for DPTF sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-03soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implement GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform, add an dummy STSX in DSDT table, read back from iotools to confirm the GPIO tx state get updated. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Reviewed-on: https://review.coreboot.org/c/30461 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-10soc/intel/cannonlake: Fix GPIO reportingDuncan Laurie
The kernel GPIO driver only expects some GPIO communities to be exported in the _CRS and it will not work correctly if the other communities are exported. CNL-LP: GPIO communities 0, 1, 4 CNL-H: GPIO communities 0, 1, 3, 4 Additionally one of the pin offset values was incorrect in GPIO community 1 for CNL-LP. This doesn't have any specific failure mode but it was found when auditing the GPIO code. Details of the kernel expected map can be found in the linux kernel at drivers/pinctrl/intel/pinctrl-cannonlake.c BUG=b:120686247 TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that pins >= 198 are not reading all zeros for the pin config registers. Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04soc/intel/cannonlake: Add DPTF ACPI codeDuncan Laurie
Define the constants that DPTF expects from the SOC in order to use the common DPTF ACPI code. For cannonlake this indicates the CPU device is called B0D4 and is at PCI address 00:04.0. Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29759 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-15soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call due to PCH requirement change from CNP PCH onwards, hence making static IRQ mapping for pci_irqs.asl and pcie.asl Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/ Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-25soc/intel/cannonlake: Enable S4 sleep state supportpraveen hodagatta pranesh
Add ACPI entry in sleepstates.asl to support S4 (hibernate). TEST: boot to Windows on CFL RVP11 & RVP8, verified hibernate functionality. Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-28soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao
Add ACPI DSDT entry for integrated Gigabit LAN controller. Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4, previous comment in southbridge.asl mention it as Function 3 that was a mistake. BUG=N/A TEST=N/A Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 06:33:41 +0000