| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-09-19 | soc/intel/cannonlake: Add PCIE IRQs | Bora Guvendik | |
| Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> | |||
| 2017-09-13 | soc/intel/cannonlake: Add common ACPI support for CNL | Lijian Zhao | |
| Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |