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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.
BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.
Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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For the internal eMMC to be used by non-chrome for installation,
the CARD device and _RMV methods are required. Without these,
other OSes does not show the eMMC as a valid installation target.
TEST= boot CNL-RVP with Tiano payload and install Windows 10
to the internal eMMC drive.
Change-Id: Icfdccd88bc113d97c2fabf4c63d8d772737a6057
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Solution: To do an additional config read to the SD controller
after the controller has been power gated (put to D3)
Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Solution: To do an additional config read to the eMMC controller
after the controller has been power gated (put to D3)
Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When system enters S0ix, system fails to power gate SD card
controller.
This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.
Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add ACPI methods for gpio, scs and pcr.
TEST=Boot to OS.
Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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