| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-10-09 | soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices | Subrata Banik | |
| This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
| 2017-09-19 | soc/intel/cannonlake: Add PCIE IRQs | Bora Guvendik | |
| Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> | |||
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index : coreboot.git | |
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