| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-10-03 | soc/intel/cannonlake: Add northbridge dsdt table | Lijian Zhao | |
| Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> | |||
| 2017-09-19 | soc/intel/cannonlake: Add PCIE IRQs | Bora Guvendik | |
| Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> | |||
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