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path: root/src/soc/intel/cannonlake/acpi.c
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2018-03-23soc/intel/cannonlake: Enable low power S0 Idle capabilityVaibhav Shankar
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. This also sets the FSPUPD to indicate the status of S0ix on the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit. Change-Id: I6214ebb61f25ef8b704e60c8474808493c92e6f6 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25292 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-26soc/intel/cannonlake: Add support for C state and P stateShaunak Saha
This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>