coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-09-20	soc/intel/cannonlake: Add PMC pci drivers	Lijian Zhao
2017-09-13	soc/intel/cannonlake: Add ramstage uart debug support	Lijian Zhao
2017-09-13	soc/intel/cannonlake: Add common ACPI support for CNL	Lijian Zhao
2017-09-06	soc/intel/cannonlake: remove duplicate uart.c from bootblock	Nick Vaccaro
2017-09-06	soc/intel/cannonlake: Add Vboot/ChromeOS support	Lijian Zhao
2017-09-01	soc/intel/cannonlake: add *spi.c files to make	Nick Vaccaro
2017-09-01	soc/intel/cannonlake: add gpio files to make	Nick Vaccaro
2017-08-25	soc/intel/cannonlake: Init UPD params based on config	Pratik Prajapati
2017-08-24	soc/intel/cannonlake: Add cpu.c and MP init support	Pratik Prajapati
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-17	soc/intel/cannonlake: Add SPI flash controller driver	Lijian Zhao
2017-08-15	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-08-15	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-08-09	soc/intel/cannonlake: Add ramstage SystemAgent support	Lijian Zhao
2017-08-07	soc/intel/cannonlake: Add memory map support	Lijian Zhao
2017-07-21	Revert "soc/intel/cannonlake: Add postcar stage support"	Martin Roth
2017-07-21	Revert "soc/intel/cannonlake: Call into FSP siliconinit"	Martin Roth
2017-07-21	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-07-21	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add microcode support	Lijian Zhao
2017-07-13	soc/intel/cannonlake: Add Makefile	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add initial dummy directory	Lijian Zhao