Age | Commit message (Collapse) | Author |
|
Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch creates a glue layer between SOC and common block IPs in terms
of PCH. All common IP blocks now can be selected based on
SOC_INTEL_COMMON_PCH_BASE config option.
BUG=none
BRANCH=b:78109109
TEST=Build and boot Cannonlake RVP and EVE.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id:I4146a040e5e43bed7ccc6cb0a7dc2271f1e7a8ea
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/26661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI to include
common xhci code block.
BUG=b:78109109
BRANCH=none
TEST=Build and boot cnlrvp
Change-Id: I7f1e59792159dae5835fbbe7fcb1604fc01893ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
TEST=Build and boot cannonlake rvp till OS.
Change-Id: I5369afd0d1d66e25d210416730a2c1c91ca8e94a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch ensures to make SMM_RESERVED_SIZE for cannonlake platform
else smm_subregion() returns 0 size.
Change-Id: I6a95a244bbcf40d672fd11d1c62e01224b2554f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
|
|
TEST=Build and boot cannonlake rvp. cpu_index() returns
correct cpu index based on caller.
Change-Id: I23f80ef455d075a14121577f401cfc7c44ba0cfa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.
BUG=b:75306520
Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.
Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
CNP-PCH
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.
Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
After adding NHLT and max98373 amp support, cnlrvp fails to boot
with error: out of memory (free_mem_ptr >= free_mem_end_ptr).
Increase HEAP_SIZE from 0x4000 to 0x8000.
BUG=None
TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp
and verify cnlrvp boots to kernel.
Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required
firmware information right after FSP-S.
TEST=Display FW information as below
>> Display FSP Version Info HOB
Reference Code - CPU = 7.1.20.52
uCode Version = 0.0.0.16
Reference Code - ME 11.0 = 7.1.20.52
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - CNL PCH = 7.1.20.52
PCH-CRID Status = Disabled
CNL PCH H A0 Hsio Version = 2.0.0.0
CNL PCH H Ax Hsio Version = 9.0.0.0
CNL PCH H Bx Hsio Version = 5.0.0.0
CNL PCH LP Ax Hsio Version = 13.0.0.0
CNL PCH LP B0 Hsio Version = 7.0.0.0
CNL PCH LP Bx Hsio Version = 6.0.0.0
CNL PCH LP Dx Hsio Version = 2.0.0.0
Reference Code - SA - System Agent = 7.1.20.52
Reference Code - MRC = 0.5.1.19
SA - PCIe Version = 7.1.20.52
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.0
SA-CRID New Value = 0.0.0.0
Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23387
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.
Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add NHLT and dt support for max98373 amp
BUG=None
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5
Signed-off-by: N, Harshapriya <harshapriya.n@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add audio NHLT support for cannonlake, reference code is implementation
in apollolake.
CQ-DEPEND=CL:*533799
BUG=None
TEST=None
Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch provides an option for non-chrome devices to make use of
FSP-T for performing cache-as-ram initialization. Majority of IOTG users
are using FSP-T for CAR implementation and aren't able to select FSP_CAR
Kconfig from SoC without conflicting with existing CAR config.
TEST=Ensure that both the Chrome platform and non Chrome OS platform
can select either CAR implementation based on Kconfig options
FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose
CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose
FSP_CAR by default.
Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add
function call to set up GPE routing in bootblock stage.
TEST=Boot up into OS, and manually check PMC GPE status
Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
BUG=b:70628116
Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22956
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:70232394
BRANCH=none
TEST=emerge-reef coreboot
emerge-glados
Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In the fast spi support implement the callback for flash_protect().
This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT
Kconfig option as well spi_flash_get_fpr_info() and separate
spi_flash.[ch].
BUG=b:69614064
Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
TEST=Build and boot cannonlake rvp.
Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Default LPSS clock need to be defined for SOC.
TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.
Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
TEST=Build and boot RVP
Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.
TEST=N/A
Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
|
|
Add common i2c support for cannonlake.
TEST=N/A
Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uses common SCS library to set up sd card.
Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add common p2sb driver support.
TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.
Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092
Increase the stack size from 4kiB to 8kiB to prevent stack overrun.
TEST=No stack overrun is observed and it boots to OS properly.
Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Cannonlake SOC support up to 16 PCI express root port.
BUG=CID 1381813;1381814;
Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
needed for CNL.
TEST=Pre-OS screen comes up and VBT is getting passed to kernel.
Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set default UART number to 2 if 32bit PCI got selected, the proper debug
print can be seen from serial port in case of switch between platforms,
especially when change to lpss uart from legacy uart or vise versa.
Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21544
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable MRC cache by default.
TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.
Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Reduce the bootblock size to 16KiB from the default 64KiB.
Not all that space is necessary.
Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1.Add common ITSS support as part of LPC driver init code.
2.Add LPC pci driver for CNL
Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Add FSP GOP config.
2. Pass VBT to FSP.
Change-Id: Icf836d683ae00cd034c853bc9ce965d4de5f7413
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,
*** CID 1380036: Control flow issues (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>> CID 1380036: Control flow issues (NO_EFFECT)
>>> "i" is converted to an unsigned type because it's compared to an unsigned constant.
80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81 if (config->PcieRpEnable[i])
82 mask |= (1 << i);
Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Adds gpio.c to romstage and ramstage.
Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS.
Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.
Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch to avoid build bot hang issue due to no
active default value for UART_FOR_CONSOLE kconfig
option.
Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21287
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Initialize UPD params based upon config
Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21175
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add initial MP init support. This boots up all CPUs.
Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add SPI driver code for the SPI flash controller, including both
fast_spi and generic_spi.
Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.
Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Look and feel update, sort the sequence in Kconfig.
Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Initialize postcar frame once finish FSP memoryinit
Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Relocate ramstage into CBMEM.
Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Microcode needs to be loaded prior to FSP initialization.
Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add basic CPU initialization for bootblock, as well as relevant headers.
Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add Cannon Lake SoC boilerplate directory with:
* SoC directory
* Base Kconfig
* Dummy cbmem.c
Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|