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Disabling interrupts and clearing errors was being done twice, once in
the `smbus_enable_iobar` reg-script, and another in `enable_smbus`.
Change-Id: I58558996bd693b302764965a5bed8b96db363833
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Haswell does not use reg-script, but does more or less the same thing.
Adapt Broadwell to ease the eventual unification with Haswell.
Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add brackets around the parameters to avoid operation order problems.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These aren't used anywhere, so get rid of them.
Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are present in Lynx Point.
Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change.
Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This makes comparisons against Haswell a bit simpler.
Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.
Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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There's no need to make so much noise when writing IOBP registers.
Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I54f96911b744f1737f7141c8a96329c95ace529d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Newer platforms use an unsigned type instead of an int. Follow suit.
Change-Id: I316864d3aed203c7c2bc962772895774fbc0c8da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The corresponding bits in PP_ON_DELAYS are reserved MBZ.
Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I049441dd9074659effc1092dce08224974d60a2c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mitigate issues presented in "Digging Into The Core of Boot" found by
"Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017.
Validate user-provided pointers using the newly-added functions.
This protects SMM from ring0 attacks.
Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.
BUG=b:159947207
Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reduces the differences between Lynxpoint and Broadwell.
Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes all redundant read microcode version implementation
from SoC directory and refer from cpu/intel/microcode/microcode.c file.
TEST=Able to get correct microcode version.
Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:
BIOS implementations must report these remapping structure types in
numerical order. i.e., All remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
So, update the corresponding code to adhere to the specification.
Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Looks like no one really knows what this bit would be useful for, nor
when it would need to be set. Especially if coreboot is setting it even
on PCI *Express* bridges. Digging through git history, nearly all
instances of setting it on PCIe bridges comes from i82801gx, for which
no reason was given as to why this would be needed. The other instances
in Intel code seem to have been, unsurprisingly, copy-pasted.
Drop all uses of this definition and rename it to avoid confusion. The
negation in the name could trick people into setting this bit again.
Tested on Asrock B85M Pro4, no visible difference.
Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Implicitly selected with MAX_CPUS != 1.
Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to the ACPI specification, version 6.3:
Accesses to the PM1 status registers are done through byte or word
accesses.
The same is said about the PM1 Enable registers. Therefore, reporting
dword-sized access is wrong and means nothing anyway. Since some other
platforms use word-sized access, use word everywhere for consistency.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel southbridges do this.
Change-Id: Id120e4a6b42168de58c396439593900a00d7e757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Found using:
diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<'
Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<'
Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'
Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ia314148abc900685d85aede3add480614fa8e99c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
|
|
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.
Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.
Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the ACPI specification, version 6.3:
OSPM accesses GPE registers through byte
accesses (regardless of their length).
So, reporting dword-sized access is wrong and means nothing anyway.
Tested on Asus P8Z77-V LX2, Windows 10 still boots.
Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
These are the simple cbmem_find() cases. Also drop the redundant
error messages.
Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Old (!PARALLEL_MP) cpu bringup uses this as the first
control to do SMM relocation.
Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Broadwell does not have any `TESGMB`, but it has a `TSEGMB`.
Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.
For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.
Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There are no side-effects in calling acpi_is_wakeup_s3()
and apm_control() is a no-op with HAVE_SMI_HANDLER=n.
Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Attempts to write to APM_CNT IO port should always be guarded
with a test to verify SMI handler has been installed.
Immediate followup removes redundant HAVE_SMI_HANDLER tests.
Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The variable SETUP_XIP_CACHE provides us a working
alternative.
Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Also remove default mb/*/fadt.c from Makefiles.
Change-Id: I6a2839c524f8311ec9a382a84066afc7d579eaca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41948
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE
so their FADT preffered_pm_profile would change from PM_MOBILE without
the added overrides here.
Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3f08b9cc34582165785063580b3356135030f63e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
|
|
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Advertising SMI triggers in FADT is only valid if we exit with
SMI installed. There has been some experiments to delay SMM
installation to OS, yet there are new platforms that allow some
configuration access only to be done inside SMM.
Splitting static HAVE_SMI_HANDLER variable helps to manage cases
where SMM might be both installed and cleared prior to entering
payload.
Change-Id: Iad92c4a180524e15199633693446a087787ad3a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'.
Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Also fix wrong 32-bit writes.
Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The allocator should take care of this.
Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.
TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
intel_backlight + acpi_video synchronize, both before and
after suspend.
Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Ifbab50ef42f0fe49dd3949db662b245c63522f2d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41599
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for auron.
Change-Id: I479bb6cb7ed4c9265325c7c8621f03454f21f467
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update processor power limit configuration parameters based on
common code base support for Intel Broadwell SoC based platforms.
BRANCH=None
BUG=None
TEST=Build for broadwell based platform
Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Unused includes found using following commande:
diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l
'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\
|MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<'
|grep -v vendor |grep -vF '.h'
Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
unused includes of <stdin.h> found using following commande:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l
'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\|
uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\|
u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\
|INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\
|INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/)
|grep '<' |grep -v vendor |grep -vF '.h'
Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pci_domain_set_resources is duplicated in all the SOCs. This change
promotes the duplicated function.
Picasso was adding it again in the northbridge patch. I decided to
promote the function instead of duplicating it.
BUG=b:147042464
TEST=Build and boot trembyle.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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|
Commands used:
perl -i -p0e 's|\/\*[*\s]*Permission[*\s]*to[*\s]*use,[*\s]*copy,[*\s]*modify,[*\s]*and.or[*\s]*distribute[*\s]*this[*\s]*software[*\s]*for[*\s]*any[*\s]*purpose[*\s]*with[*\s]*or[*\s]*without[*\s]*fee[*\s]*is[*\s]*hereby[*\s]*granted,[*\s]*provided[*\s]*that[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice[*\s]*and[*\s]*this[*\s]*permission[*\s]*notice[*\s]*appear[*\s]*in[*\s]*all[*\s]*copies.[*\s]*THE[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED[*\s]*.*AS[*\s]*IS.*[*\s]*AND[*\s]*THE[*\s]*AUTHOR[*\s]*DISCLAIMS[*\s]*ALL[*\s]*WARRANTIES[*\s]*WITH[*\s]*REGARD[*\s]*TO[*\s]*THIS[*\s]*SOFTWARE[*\s]*INCLUDING[*\s]*ALL[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY[*\s]*AND[*\s]*FITNESS.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL[*\s]*THE[*\s]*AUTHOR[*\s]*BE[*\s]*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*SPECIAL,[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*OR[*\s]*ANY[*\s]*DAMAGES[*\s]*WHATSOEVER[*\s]*RESULTING[*\s]*FROM[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA[*\s]*OR[*\s]*PROFITS,[*\s]*WHETHER[*\s]*IN[*\s]*AN[*\s]*ACTION[*\s]*OF[*\s]*CONTRACT,[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHER[*\s]*TORTIOUS[*\s]*ACTION,[*\s]*ARISING[*\s]*OUT[*\s]*OF[*\s]*OR[*\s]*IN[*\s]*CONNECTION[*\s]*WITH[*\s]*THE[*\s]*USE[*\s]*OR[*\s]*PERFORMANCE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE.[*\s]*\*\/|/* SPDX-License-Identifier: ISC */|s' $(cat filelist)
perl -i -p0e 's|(\#\#*)\s*Permission[\#\s]*to[\#\s]*use,[\#\s]*copy,[\#\s]*modify,[\#\s]*and.or[\#\s]*distribute[\#\s]*this[\#\s]*software[\#\s]*for[\#\s]*any[\#\s]*purpose[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*fee[\#\s]*is[\#\s]*hereby[\#\s]*granted,[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice[\#\s]*and[\#\s]*this[\#\s]*permission[\#\s]*notice[\#\s]*appear[\#\s]*in[\#\s]*all[\#\s]*copies.[\#\s]*THE[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED[\#\s]*.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*THE[\#\s]*AUTHOR[\#\s]*DISCLAIMS[\#\s]*ALL[\#\s]*WARRANTIES[\#\s]*WITH[\#\s]*REGARD[\#\s]*TO[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*INCLUDING[\#\s]*ALL[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY[\#\s]*AND[\#\s]*FITNESS.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL[\#\s]*THE[\#\s]*AUTHOR[\#\s]*BE[\#\s]*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*SPECIAL,[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*OR[\#\s]*ANY[\#\s]*DAMAGES[\#\s]*WHATSOEVER[\#\s]*RESULTING[\#\s]*FROM[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA[\#\s]*OR[\#\s]*PROFITS,[\#\s]*WHETHER[\#\s]*IN[\#\s]*AN[\#\s]*ACTION[\#\s]*OF[\#\s]*CONTRACT,[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHER[\#\s]*TORTIOUS[\#\s]*ACTION,[\#\s]*ARISING[\#\s]*OUT[\#\s]*OF[\#\s]*OR[\#\s]*IN[\#\s]*CONNECTION[\#\s]*WITH[\#\s]*THE[\#\s]*USE[\#\s]*OR[\#\s]*PERFORMANCE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE.\s(\#* *\n)*|\1 SPDX-License-Identifier: ISC\n\n|s' $(cat filelist)
perl -i -p0e 's|\/\*[*\s]*Redistribution[*\s]*and[*\s]*use[*\s]*in[*\s]*source[*\s]*and[*\s]*binary[*\s]*forms,[*\s]*with[*\s]*or[*\s]*without[*\s]*modification,[*\s]*are[*\s]*permitted[*\s]*provided[*\s]*that[*\s]*the[*\s]*following[*\s]*conditions[*\s]*are[*\s]*met:[*\s]*[1. ]*Redistributions[*\s]*of[*\s]*source[*\s]*code[*\s]*must[*\s]*retain[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer.[*\s]*[*\s]*[2. ]*Redistributions[*\s]*in[*\s]*binary[*\s]*form[*\s]*must[*\s]*reproduce[*\s]*the[*\s]*above[*\s]*copyright[*\s]*notice,[*\s]*this[*\s]*list[*\s]*of[*\s]*conditions[*\s]*and[*\s]*the[*\s]*following[*\s]*disclaimer[*\s]*in[*\s]*the[*\s]*documentation[*\s]*and.or[*\s]*other[*\s]*materials[*\s]*provided[*\s]*with[*\s]*the[*\s]*distribution.[*\s]*[3. ]*.*used[*\s]*to[*\s]*endorse[*\s]*or[*\s]*promote[*\s]*products[*\s]*derived[*\s]*from[*\s]*this[*\s]*software[*\s]*without[*\s]*specific[*\s]*prior[*\s]*written[*\s]*permission.[*\s]*THIS[*\s]*SOFTWARE[*\s]*IS[*\s]*PROVIDED.*AS[*\s]*IS.*[*\s]*AND[*\s]*ANY[*\s]*EXPRESS[*\s]*OR[*\s]*IMPLIED[*\s]*WARRANTIES,[*\s]*INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*THE[*\s]*IMPLIED[*\s]*WARRANTIES[*\s]*OF[*\s]*MERCHANTABILITY.*FITNESS[*\s]*FOR[*\s]*A[*\s]*PARTICULAR[*\s]*PURPOSE.*ARE[*\s]*DISCLAIMED.[*\s]*IN[*\s]*NO[*\s]*EVENT[*\s]*SHALL.*LIABLE[*\s]*FOR[*\s]*ANY[*\s]*DIRECT,[*\s]*INDIRECT,[*\s]*INCIDENTAL,[*\s]*SPECIAL,[*\s]*EXEMPLARY,[*\s]*OR[*\s]*CONSEQUENTIAL[*\s]*DAMAGES[*\s]*.INCLUDING,[*\s]*BUT[*\s]*NOT[*\s]*LIMITED[*\s]*TO,[*\s]*PROCUREMENT[*\s]*OF[*\s]*SUBSTITUTE[*\s]*GOODS[*\s]*OR[*\s]*SERVICES;[*\s]*LOSS[*\s]*OF[*\s]*USE,[*\s]*DATA,[*\s]*OR[*\s]*PROFITS;[*\s]*OR[*\s]*BUSINESS[*\s]*INTERRUPTION.[*\s]*HOWEVER[*\s]*CAUSED[*\s]*AND[*\s]*ON[*\s]*ANY[*\s]*THEORY[*\s]*OF[*\s]*LIABILITY,[*\s]*WHETHER[*\s]*IN[*\s]*CONTRACT,[*\s]*STRICT[*\s]*LIABILITY,[*\s]*OR[*\s]*TORT[*\s]*.INCLUDING[*\s]*NEGLIGENCE[*\s]*OR[*\s]*OTHERWISE.[*\s]*ARISING[*\s]*IN[*\s]*ANY[*\s]*WAY[*\s]*OUT[*\s]*OF[*\s]*THE[*\s]*USE[*\s]*OF[*\s]*THIS[*\s]*SOFTWARE,[*\s]*EVEN[*\s]*IF[*\s]*ADVISED[*\s]*OF[*\s]*THE[*\s]*POSSIBILITY[*\s]*OF[*\s]*SUCH[*\s]*DAMAGE.[*\s]*\*\/|/* SPDX-License-Identifier: BSD-3-Clause */|s' $(cat filelist) $1
perl -i -p0e 's|(\#\#*) *Redistribution[\#\s]*and[\#\s]*use[\#\s]*in[\#\s]*source[\#\s]*and[\#\s]*binary[\#\s]*forms,[\#\s]*with[\#\s]*or[\#\s]*without[\#\s]*modification,[\#\s]*are[\#\s]*permitted[\#\s]*provided[\#\s]*that[\#\s]*the[\#\s]*following[\#\s]*conditions[\#\s]*are[\#\s]*met:[\#\s]*[*1. ]*Redistributions[\#\s]*of[\#\s]*source[\#\s]*code[\#\s]*must[\#\s]*retain[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer.[\#\s]*[*2. ]*Redistributions[\#\s]*in[\#\s]*binary[\#\s]*form[\#\s]*must[\#\s]*reproduce[\#\s]*the[\#\s]*above[\#\s]*copyright[\#\s]*notice,[\#\s]*this[\#\s]*list[\#\s]*of[\#\s]*conditions[\#\s]*and[\#\s]*the[\#\s]*following[\#\s]*disclaimer[\#\s]*in[\#\s]*the[\#\s]*documentation[\#\s]*and.or[\#\s]*other[\#\s]*materials[\#\s]*provided[\#\s]*with[\#\s]*the[\#\s]*distribution.[\#\s]*[\#\s]*[*3. ]*.*used[\#\s]*to[\#\s]*endorse[\#\s]*or[\#\s]*promote[\#\s]*products[\#\s]*derived[\#\s]*from[\#\s]*this[\#\s]*software[\#\s]*without[\#\s]*specific[\#\s]*prior[\#\s]*written[\#\s]*permission.[\#\s]*THIS[\#\s]*SOFTWARE[\#\s]*IS[\#\s]*PROVIDED.*AS[\#\s]*IS.*[\#\s]*AND[\#\s]*ANY[\#\s]*EXPRESS[\#\s]*OR[\#\s]*IMPLIED[\#\s]*WARRANTIES,[\#\s]*INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*THE[\#\s]*IMPLIED[\#\s]*WARRANTIES[\#\s]*OF[\#\s]*MERCHANTABILITY.*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.*ARE[\#\s]*DISCLAIMED.[\#\s]*IN[\#\s]*NO[\#\s]*EVENT[\#\s]*SHALL.*LIABLE[\#\s]*FOR[\#\s]*ANY[\#\s]*DIRECT,[\#\s]*INDIRECT,[\#\s]*INCIDENTAL,[\#\s]*SPECIAL,[\#\s]*EXEMPLARY,[\#\s]*OR[\#\s]*CONSEQUENTIAL[\#\s]*DAMAGES[\#\s]*.INCLUDING,[\#\s]*BUT[\#\s]*NOT[\#\s]*LIMITED[\#\s]*TO,[\#\s]*PROCUREMENT[\#\s]*OF[\#\s]*SUBSTITUTE[\#\s]*GOODS[\#\s]*OR[\#\s]*SERVICES;[\#\s]*LOSS[\#\s]*OF[\#\s]*USE,[\#\s]*DATA,[\#\s]*OR[\#\s]*PROFITS;[\#\s]*OR[\#\s]*BUSINESS[\#\s]*INTERRUPTION.[\#\s]*HOWEVER[\#\s]*CAUSED[\#\s]*AND[\#\s]*ON[\#\s]*ANY[\#\s]*THEORY[\#\s]*OF[\#\s]*LIABILITY,[\#\s]*WHETHER[\#\s]*IN[\#\s]*CONTRACT,[\#\s]*STRICT[\#\s]*LIABILITY,[\#\s]*OR[\#\s]*TORT[\#\s]*.INCLUDING[\#\s]*NEGLIGENCE[\#\s]*OR[\#\s]*OTHERWISE.[\#\s]*ARISING[\#\s]*IN[\#\s]*ANY[\#\s]*WAY[\#\s]*OUT[\#\s]*OF[\#\s]*THE[\#\s]*USE[\#\s]*OF[\#\s]*THIS[\#\s]*SOFTWARE,[\#\s]*EVEN[\#\s]*IF[\#\s]*ADVISED[\#\s]*OF[\#\s]*THE[\#\s]*POSSIBILITY[\#\s]*OF[\#\s]*SUCH[\#\s]*DAMAGE.\s(\#* *\n)*|\1 SPDX-License-Identifier: BSD-3-Clause\n\n|s' $(cat filelist)
Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Copyright notices are best stored in AUTHORS
Change-Id: Ib9025c58987ee2f7db600e038f5d3e4edc69aacc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41203
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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vboot_recovery_mode_enabled() was recently changed to assert() when it
is called before vboot logic has run, because we cannot determine
whether we're going to be in recovery mode at that point and we wanted
to flush out existing uses that pretended that we could. Turns out there
are a bunch of uses like that, and there is some code that is shared
across configurations that can and those that can't.
This patch cleans them up to either remove checks that cannot return
true, or add explicit Kconfig guards to clarify that the code is shared.
This means that using a separate recovery MRC cache is no longer
supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already
been broken with CB:38780, but with this patch those boards will boot
again using their normal MRC caches rather than just die). Skipping the
MRC cache and always regenerating from scratch in recovery mode is
likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE.
For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and
that is unlikely to change in the future so we will just hardcode that
fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed
to work around this issue).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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.acpi_inject_dsdt() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
acpi_inject_dsdt as const.
Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Some of the revision 4 FADT fields were already updated to ACPI
spec revision 6, but not all of them. In addition the advertised
FADT revision was 3.
Implement all fields as defined in version 6 and bump the advertised
FADT revision to 6.
Also set all used access_size fields and x_gpe0_blk to sane values
as Windows 10 verifies those fields starting with FADT revision 5.
Fixes: https://ticket.coreboot.org/issues/109
Tested on Windows 10.
Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.
Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.
Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8995372760543e9cf2c845019f7a063046c55e9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Add framework to generate ACPI methods in SSDT for
screen backlight control. Adjust params for gtt_ methods
to match prototypes in i915.h and avoid conflicts.
To make use of this, individual boards will need to
include default_brightness_levels.asl in their dsdt, as
well as add 'register "gfx" = "GMA_STATIC_DISPLAYS(0)"' to
their devicetree.
Change-Id: If93b7690ef36b5d19ca43957e8a1bef91ec5821d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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After measured boot is decoupled from verified boot in CB:35077,
vboot_platform_is_resuming() is never vboot-specific, thus it is
renamed to platform_is_resuming() and declared in bootmode.h.
Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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The PWM-granularity chicken bit in the Wildcat Point and Lynx Point
PCHs has actually the opposite meaning of the one for Sunrise Point
and later. When the bit is set, we get a divider of 16, when it's
unset 128. Flip the bit!
Change-Id: I1dbde1915d8b269c11643a1636565a560eb07334
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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