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Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.
Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The only functional difference is the use of stack guards.
Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Call the raminit from a common location instead of from the mainboard
specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To improve the bootflow, the scope of the pei_data needs to be
extended.
Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some similar calls to postcar_frame_add_mtrr() were added in the
meantime or were under review while postcar_frame_add_romcache()
was introduced.
Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.
Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Platforms moved to POSTCAR_STAGE so these are no longer used.
Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This does the following:
- Reuse the cpu/intel/car/non-evict CAR setup and exit.
- Use postcar_frame functions to set up the postcar frame
Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change "mttrs" to mtrrs.
Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of writing out '__attribute__((weak))' use a shorter form.
Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This callback was only required for a single mainboard, and it can
easily be moved to mainboard-specific code. This patch removes it from
the global namespace and isolates it to the Jecht board. (This makes
it easier to separate vboot and chromeos code in a later patch.)
Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Fix the following error and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
WARNING: line over 80 characters
WARNING: storage class should be at the beginning of the declaration
WARNING: adding a line without newline at end of file
WARNING: __func__ should be used instead of gcc specific __FUNCTION__
WARNING: Comparisons should place the constant on the right side of the test
TEST=None
Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18885
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the following errors and warnings detected by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
TEST=None
Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18884
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: spaces required around that '>=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required before the open parenthesis '('
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line
False positives are generated for the following test:
WARNING: space prohibited between function name and open parenthesis '('
in both pei_data.h and pei_wrapper.h
TEST=None
Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18872
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The same pattern was being used throughout the code base
for initializing the romstage handoff structure. Provide
a helper function to initialize the structure with the S3
resume state then utilize it at all the existing call sites.
Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17646
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All current implementations of ramstage_cache_invalid() were just
resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE
Kconfig option. Move that behavior to a single implementation
within prog_loaders.c which removes duplication.
Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17184
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15461
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This removes the dependency on chromeos and vboot for the sw write protect state
function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
both reflect this change and become consistent with the definition of
get_write_protect_state that is already in use.
Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It's guarded by a non-standard configuration option, so didn't trigger.
Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10623
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Builds with CHROMEOS fail due to missing includes.
Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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This patch fixes the use of the recovery button, and the value is stored
in a SATA controller scratch register.
BUG=chrome-os-partner:35241
BRANCH=none
TEST=Use recovery button and run firmware_RecoveryButton
Change-Id: Ia06f147c7e44d6c4eea2c2e4f502c233c956ee9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34c7ee922a9602b3448a72cd669fd68feeed1bba
Original-Change-Id: I1667c7f188b0f87c4bc7caa82f9c977b2b4c0611
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241772
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9811
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Serial port on ITE 8772 SuperIO must be initialized before
console_init is called. So the pre console init callback
is added to let mainboard code do proper initialization.
Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1
Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/227933
Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log
Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13
Reviewed-on: http://review.coreboot.org/8966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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No reason to carry timestamps on CAR stack, as implementation
of timestamps internally stashes on CAR_GLOBAL table and migrates
those to CBMEM.
Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8022
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.
Timestamp implementation for ARMv7
Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.
The ARM implementation uses the monotonic timer.
Original-Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps
Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)
Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.
- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic
Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)
broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)
broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)
broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)
broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)
broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)
broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)
broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)
broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)
broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)
broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)
broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)
broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)
broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)
broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)
Squashed 15 commits for broadwell support.
Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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broadwell: Import files from haswell/lynxpoint into soc/broadwell
Reviewed-on: https://chromium-review.googlesource.com/198425
(cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af)
broadwell: Unify and clean up license
Reviewed-on: https://chromium-review.googlesource.com/198426
(cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d)
broadwell: pch.h: split PM into new header
Reviewed-on: https://chromium-review.googlesource.com/198427
(cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373)
broadwell: pch.h: split RCBA into new header
Reviewed-on: https://chromium-review.googlesource.com/198428
(cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135)
broadwell: pch.h: split SATA into new header
Reviewed-on: https://chromium-review.googlesource.com/198429
(cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71)
broadwell: pch.h: split SPI into new header
Reviewed-on: https://chromium-review.googlesource.com/198550
(cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14)
broadwell: pch.h: split SerialIO into new header
Reviewed-on: https://chromium-review.googlesource.com/198551
(cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6)
broadwell: pch.h: split LPC into new header
Reviewed-on: https://chromium-review.googlesource.com/198552
(cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102)
broadwell: pch.h: split GPIO into new header and clean up
Reviewed-on: https://chromium-review.googlesource.com/198553
(cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5)
broadwell: pch.h: split USB into new headers
Reviewed-on: https://chromium-review.googlesource.com/198554
(cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068)
broadwell: Split IOBP into separate files
Reviewed-on: https://chromium-review.googlesource.com/198734
(cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600)
broadwell: smbus: Extract common code and split header
Reviewed-on: https://chromium-review.googlesource.com/198735
(cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d)
broadwell: Create iomap.h header with platform base addresses
Reviewed-on: https://chromium-review.googlesource.com/198736
(cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee)
broadwell: Add header for platform PCI devices
Reviewed-on: https://chromium-review.googlesource.com/198737
(cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500)
broadwell: Split SMM related defines/prototypes to new header
Reviewed-on: https://chromium-review.googlesource.com/198738
(cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4)
broadwell: cpu.h: Split MSR defines to separate header
Reviewed-on: https://chromium-review.googlesource.com/198739
(cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805)
broadwell: Create romstage header file
Reviewed-on: https://chromium-review.googlesource.com/198740
(cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21)
broadwell: Create ram stage header file
Reviewed-on: https://chromium-review.googlesource.com/198741
(cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621)
broadwell: Add reference code data interface
Reviewed-on: https://chromium-review.googlesource.com/198743
(cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95)
broadwell: Clean up ACPI NVS region
Reviewed-on: https://chromium-review.googlesource.com/198897
(cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14)
broadwell: Move CTDP ACPI methods to new file
Reviewed-on: https://chromium-review.googlesource.com/198898
(cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2)
broadwell: Split EHCI and XHCI ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/198899
(cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca)
broadwell: ACPI: Clean up SerialIO ACPI code
Reviewed-on: https://chromium-review.googlesource.com/198910
(cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35)
broadwell: ACPI: Remove special handling of LPT-LP chipset
Reviewed-on: https://chromium-review.googlesource.com/198911
(cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6)
broadwell: ACPI: Clean up use of base address defines
Reviewed-on: https://chromium-review.googlesource.com/198912
(cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75)
broadwell: ACPI: Clean up and fix formatting
Reviewed-on: https://chromium-review.googlesource.com/198913
(cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050)
broadwell: Add header for ACPI defines and prototypes
Reviewed-on: https://chromium-review.googlesource.com/198914
(cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9)
broadwell: Add reset_system function and header
Reviewed-on: https://chromium-review.googlesource.com/198915
(cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef)
broadwell: Move PCODE MMIO defines to systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198916
(cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f)
broadwell: Unify chip.h and add chip.c
Reviewed-on: https://chromium-review.googlesource.com/198917
(cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1)
broadwell: Rename HASWELL_BCLK to CPU_BCLK
Reviewed-on: https://chromium-review.googlesource.com/198918
(cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1)
broadwell: Clean up broadwell/cpu.h
Reviewed-on: https://chromium-review.googlesource.com/198919
(cherry picked from commit 17353803babc8ace279e105c012130678226144e)
broadwell: Clean up broadwell/systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198920
(cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae)
broadwell: Clean up broadwell/pch.h
Reviewed-on: https://chromium-review.googlesource.com/198921
(cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b)
broadwell: Clean up management engine driver
Reviewed-on: https://chromium-review.googlesource.com/198922
(cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72)
broadwell: Add common CPUID and PCI Device ID defines
Reviewed-on: https://chromium-review.googlesource.com/198923
(cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8)
broadwell: Clean up and expand report_platform
Reviewed-on: https://chromium-review.googlesource.com/198924
(cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022)
broadwell: Clean up the bootblock code
Reviewed-on: https://chromium-review.googlesource.com/198925
(cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c)
broadwell: Clean up ramstage device and driver operations
Reviewed-on: https://chromium-review.googlesource.com/199180
(cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569)
broadwell: Clean up XHCI and EHCI ramstage drivers
Reviewed-on: https://chromium-review.googlesource.com/199181
(cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d)
broadwell: Clean up gpio handling code
Reviewed-on: https://chromium-review.googlesource.com/199182
(cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20)
broadwell: Clean up the PCH generic code
Reviewed-on: https://chromium-review.googlesource.com/199183
(cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff)
broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c
Reviewed-on: https://chromium-review.googlesource.com/199184
(cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7)
broadwell: Clean up pmutil.c
Reviewed-on: https://chromium-review.googlesource.com/199185
(cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84)
broadwell: pmutil: Add new acpi_sci_irq() function
Reviewed-on: https://chromium-review.googlesource.com/199186
(cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5)
broadwell: Clean up HDA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199187
(cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d)
broadwell: Clean up cache_as_ram assembly
Reviewed-on: https://chromium-review.googlesource.com/199188
(cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d)
broadwell: romstage: Separate stack helper functions
Reviewed-on: https://chromium-review.googlesource.com/199189
(cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad)
broadwell: Add function to read WPSR from SPI
Reviewed-on: https://chromium-review.googlesource.com/199190
(cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a)
broadwell: Clean up SMBUS code in romstage and ramstage
Reviewed-on: https://chromium-review.googlesource.com/199191
(cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa)
broadwell: SPI: Clean up romstage and ramstage code
Reviewed-on: https://chromium-review.googlesource.com/199192
(cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf)
broadwell: Clean up PCIe root port ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199193
(cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e)
broadwell: Clean up minihd ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199194
(cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e)
broadwell: Update romstage main to follow baytrail format
Reviewed-on: https://chromium-review.googlesource.com/199361
(cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd)
broadwell: Add CPU set_max_freq function for romstage
Reviewed-on: https://chromium-review.googlesource.com/199362
(cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6)
broadwell: romstage: Add chipset_power_state implementation
Reviewed-on: https://chromium-review.googlesource.com/199363
(cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c)
broadwell: romstage: Convert systemagent init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199364
(cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2)
broadwell: romstage: Convert pch init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199365
(cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c)
broadwell: elog: Use chipset_power_state for events
Reviewed-on: https://chromium-review.googlesource.com/199366
(cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9)
broadwell: Clean up SATA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199367
(cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8)
broadwell: Update ramstage graphics driver to support broadwell
Reviewed-on: https://chromium-review.googlesource.com/199368
(cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281)
broadwell: Update raminit to follow baytrail layout
Reviewed-on: https://chromium-review.googlesource.com/199369
(cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523)
broadwell: Update and unify the finalize steps
Reviewed-on: https://chromium-review.googlesource.com/199390
(cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa)
broadwell: Clean up SMM code
Reviewed-on: https://chromium-review.googlesource.com/199391
(cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd)
broadwell: Clean up LPC ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199392
(cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e)
broadwell: Clean up systemagent ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199393
(cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3)
broadwell: Move C-state configuration information to acpi.c
Reviewed-on: https://chromium-review.googlesource.com/199394
(cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990)
broadwell: Clean up CPU ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199395
(cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969)
broadwell: Do not reserve SMM relocation region
Reviewed-on: https://chromium-review.googlesource.com/199402
(cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c)
broadwell: Add an early ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199403
(cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3)
broadwell: Support for second reference code binary
Reviewed-on: https://chromium-review.googlesource.com/199404
(cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2)
broadwell: Clean up serialio init code
Reviewed-on: https://chromium-review.googlesource.com/199405
(cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489)
broadwell: acpi: Add function to fill out FADT
Reviewed-on: https://chromium-review.googlesource.com/199406
(cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74)
broadwell: Update C-state table creation
Reviewed-on: https://chromium-review.googlesource.com/199407
(cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063)
broadwell: acpi: Clean up acpi table creation code
Reviewed-on: https://chromium-review.googlesource.com/199408
(cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146)
broadwell: acpi: Add ACPI table create helper functions
Reviewed-on: https://chromium-review.googlesource.com/199409
(cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c)
broadwell: Add soc/intel/broadwell Makefiles
Reviewed-on: https://chromium-review.googlesource.com/199410
(cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc)
broadwell: Add Kconfig for broadwell soc
Reviewed-on: https://chromium-review.googlesource.com/199411
(cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe)
Squashed 78 commits for broadwell that form a solid code base.
Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6964
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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