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2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-01intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-03-27device/pciexp_device: Convert LTR non-snoop/snoop value into common macroSubrata Banik
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-21{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-01soc/intel/broadwell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26583 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08intel/broadwell: Add option to enable/disable the PCIe AER capabilityYouness Alaoui
The Advanced Error Reporting capability was hardcoded in the PCIe extended capability list, but it might not always be possible. The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08intel/broadwell: If L1 Sub state is disabled, do not set capabilityYouness Alaoui
I finally found out why disabling the L1 sub state option did not prevent some NVMe drives from locking up in L1 substate. I expect that the disabled L1 substate initialization that coreboot does is negated because Linux might itself configure it if it finds the capability enabled on the PCIe root port. Removing the capability from the PCIe root port when L1 sub states are disabled in the configuration should fix the problem. This was not tested because it's a difficult issue to reproduce and I do not have the problematic hardware that caused it anymore. Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-03-17soc/intel/broadwell: Fix other issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent WARNING: line over 80 characters WARNING: storage class should be at the beginning of the declaration WARNING: adding a line without newline at end of file WARNING: __func__ should be used instead of gcc specific __FUNCTION__ WARNING: Comparisons should place the constant on the right side of the test TEST=None Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18885 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/broadwell: Add int to unsignedLee Leahy
Fix the following issue detected by checkpatch: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=None Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18873 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-31intel/broadwell: fix typoPatrick Georgi
(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents "case 3" below from ever happening) Change-Id: Id90655c39ff53da9569441278bbf73497d643480 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1293139 Reviewed-on: https://review.coreboot.org/15965 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2015-12-20soc/intel/broadwell: Init var before use, only use when neededMartin Roth
root_port_init_config() pcie.c wasn't initializing a variable before passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the uninitialized value into a register. In theory, the register would only be used if data was being written, and pch_iobp_exec() was being used to read the data, not write it, so this change shouldn't have any practical effect. Fixes coverity error: CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT) Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12778 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors. BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9501 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
When disabling PCIe ports skip steps if no card is detected. This prevents the loop from timing out on each empty slot. BUG=chrome-os-partner:31424 BRANCH=broadwell TEST=build and boot on samus, check that this code is no longer timing out when disabling PCIe ports Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240851 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9489 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle. This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode. BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
BUG=chrome-os-partner:31424 TEST=Build a image and run on Samus proto boards to confirm if the settings are applied correctly. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I9147da86ce26ce7ef1c7034bc3dde0b27b63befa Original-Commit-Id: 1717505a3fdf41c5972b1c929872577247f9e3b5 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I8138507506771148420a585fd12897a3bfe91916 Original-Reviewed-on: https://chromium-review.googlesource.com/221387 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 Reviewed-on: http://review.coreboot.org/9267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02Broadwell: Synchronize for power management with FRCKenji Chen
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build an image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRCKenji Chen
OBFF: Disable it by clearing bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommended setting. BUG=None TEST=Build an image and check the setting are applied correctly on Samus. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Revise programming flow for write-once registersKenji Chen
Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9 Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 Reviewed-on: http://review.coreboot.org/9209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Configure IOSF Port and Grant CountKenji Chen
Synchronize the code with FRC. Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreboot image and run on Samus to confirm the setting is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Update PCIe configuration to follow BWGKane Chen
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-08intel/broadwell: Spelling fixesMartin Roth
Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7702 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-22broadwell: add new intel SOCDuncan Laurie
broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit 17353803babc8ace279e105c012130678226144e) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 17:07:58 +0000