coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-12-03	src: Remove redundant use of ACPI offset(0)	Elyes HAOUAS
	IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13	soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl`	Angel Pons
	This is merely to ease diffing Lynx Point and Broadwell ASL code. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46779 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13	soc/intel/broadwell/pch/acpi: Clean up cosmetics	Angel Pons
	Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl`	Angel Pons
	Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: If5f1feb0cd43fe1e0514b4e3fa766da60e2b7603 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46773 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell: Include EC and IRQ links ACPI early	Angel Pons
	Other southbridges such as Lynx Point do it. This eases merging later. Change-Id: I10196bbc44ce859c2747755845378351f45944ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell/pch: Use common PCIe ACPI code	Angel Pons
	Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46763 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell/pch/acpi: Add PCIe register offsets	Angel Pons
	These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code. Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell: Use common irqlinks.asl	Angel Pons
	Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46759 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs	Angel Pons
	Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs) added these IRQs for Lynx Point and earlier southbridges. Follow suit for Broadwell, since it also supports them. Vendor firmware of the Asus X555LAB laptop also contains these IRQs, as per the disassembled DSDT. Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04	soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint	Angel Pons
	Drop unnecessary smbus.asl in favor of southbridge common code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03	soc/intel/broadwell: Relocate PCH ACPI files	Angel Pons
	Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>